imx8mq-bio.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2018 Boundary Devices
 */

/dts-v1/;

/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;

#include "fsl-imx8mq.dtsi"

#if 0
#define MIPI_ON_DCSS
#endif

#if 0
#define RM68200
#endif

#if 1
#define HDMI_STATUS	"okay"
#else
#define HDMI_STATUS	"disabled"
#endif

#if 0
#define MIPI_DSI_STATUS	"okay"
#else
#define MIPI_DSI_STATUS	"disabled"
#endif

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	iomuxc_pinctrl: iomuxc-pinctrlgrp {
	};
};

&iomuxc_pinctrl {
	pinctrl_backlight: backlightgrp {
		fsl,pins = <
#define GPIRQ_BKLIT_ERR	<&gpio4 19 IRQ_TYPE_LEVEL_HIGH>
			MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19		0x19
		>;
	};

	pinctrl_bt_rfkill: bt-rfkillgrp {
		fsl,pins = <
#define GP_BT_RFKILL_RESET	<&gpio3 19 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19		0x19
		>;
	};

	pinctrl_gpio_keys: gpio_keysgrp {
		fsl,pins = <
#define GP_GPIOKEY_POWER	<&gpio1 7 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19	/* sw3 */
			/* J1 connector */
#define GP_GPIOKEY_J1_P2	<&gpio4 1 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1			0x19	/* Pin 2 */
#define GP_GPIOKEY_J1_P3	<&gpio5 5 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5		0x19	/* Pin 3 */
#define GP_GPIOKEY_J1_P4	<&gpio4 3 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3		0x19	/* Pin 4 */
#define GP_GPIOKEY_J1_P5	<&gpio4 4 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4		0x19	/* Pin 5 */
#define GP_GPIOKEY_J1_P6	<&gpio4 5 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5		0x19	/* Pin 6 */
#define GP_GPIOKEY_J1_P7	<&gpio4 6 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6		0x19	/* Pin 7 */
#define GP_GPIOKEY_J1_P8	<&gpio4 7 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7		0x19	/* Pin 8 */
#define GP_GPIOKEY_J1_P9	<&gpio4 8 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8		0x19	/* Pin 9 */
			/* J17 connector */
#define GP_GPIOKEY_J17_P2	<&gpio4 0 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0		0x19	/* Pin 2 */
#define GP_GPIOKEY_J17_P3	<&gpio1 3 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19	/* Pin 3 */
#define GP_GPIOKEY_J17_P4	<&gpio1 10 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19	/* Pin 4 */
#define GP_GPIOKEY_J17_P5	<&gpio5 10 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10		0x19	/* Pin 5 */
#define GP_GPIOKEY_J17_P6	<&gpio1 1 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x19	/* pin 6 */

			/* J21 connector */
#define GP_GPIOKEY_J21_P2	<&gpio3 4 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4		0x19	/* Pin 2 */
#define GP_GPIOKEY_J21_P3	<&gpio3 15 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x19	/* Pin 3 */
#define GP_GPIOKEY_J21_P4	<&gpio3 11 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11		0x19	/* Pin 4 */
#define GP_GPIOKEY_J21_P5	<&gpio3 10 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10		0x19	/* Pin 5 */
#define GP_GPIOKEY_J21_P6	<&gpio3 9 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9		0x19	/* Pin 6 */
#define GP_GPIOKEY_J21_P7	<&gpio3 8 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8		0x19	/* Pin 7 */
#define GP_GPIOKEY_J21_P8	<&gpio3 7 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7		0x19	/* Pin 8 */
#define GP_GPIOKEY_J21_P9	<&gpio3 6 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6		0x19	/* Pin 9 */
#define GP_GPIOKEY_J21_P10	<&gpio1 5 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5		0x19	/* Pin 10 */
		>;
	};

	pinctrl_hog: hoggrp {
		fsl,pins = <
			/* J19 Pin 2, WL_WAKE */
			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0xd6
			/* J19 Pin 4, WL_IRQ, not needed for Silex */
			MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21		0xd6
			/* J19 Pin 41, BT_CLK_REQ */
			MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22		0xd6
			/* J19 Pin 42, BT_HOST_WAKE */
			MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25		0xd6

			/* test points */
			MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16		0x19	/* TP29 */
			MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0			0x19	/* TP30 */
			MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16		0x19	/* TP31 */
			MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT			0x19	/* TP32 */
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA			0x4000007f
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA			0x4000007f
		>;
	};

	pinctrl_i2c2_csi1: i2c2-csi1grp {
		fsl,pins = <
#define GP_CSI1_MIPI_PWDN	<&gpio4 25 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25		0x61
#define GP_CSI1_MIPI_RESET	<&gpio4 24 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24		0x61
			/* Clock for CSI1 */
			MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2	0x59
		>;
	};

	pinctrl_i2c2_sn65dsi83: i2c2-sn65dsi83 {
		fsl,pins = <
#define GPIRQ_I2C2_SN65DSI83	<&gpio4 28 IRQ_TYPE_LEVEL_LOW>
			MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28	0x16
#define GP_I2C2_SN65DSI83_EN	<&gpio3 14 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14	0x26
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x4000007f
		>;
	};

	pinctrl_i2c3_rv4162: i2c3-rv4162grp {
		fsl,pins = <
#define GPIRQ_RV4162		<&gpio1 6 IRQ_TYPE_LEVEL_LOW>
			MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x49
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x4000007f
			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x4000007f
		>;
	};

	pinctrl_i2c4_gt911: i2c4-gt911grp {
		fsl,pins = <
#define GPIRQ_GT911 		<&gpio3 12 IRQ_TYPE_LEVEL_HIGH>
#define GP_GT911_IRQ 		<&gpio3 12 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12	0xd6
			/* driver writes levels, instead of active/inactive */
#define GP_GT911_RESET		<&gpio3 13 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13	0x49
		>;
	};

	pinctrl_i2c4_ft5x06: i2c4-ft5x06grp {
		fsl,pins = <
#define GPIRQ_I2C4_FT5X06	<&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C4_FT5X06_WAKE	<&gpio3 12 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12	0x49
#define GP_I2C4_FT5X06_RESET	<&gpio3 13 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13	0x49
		>;
	};

	pinctrl_i2c4_st1633: i2c4-st1633grp {
		fsl,pins = <
#define GPIRQ_ST1633 		<&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_ST1633_IRQ 		<&gpio3 12 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12	0xd6
#define GP_ST1633_RESET		<&gpio3 13 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13	0x49
		>;
	};

	pinctrl_mipi_com50h5n03ulc: mipi-com50h5n03ulcgrp {
		fsl,pins = <
#define GP_MIPI_RESET	<&gpio3 14 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14	0x16
		>;
	};

	pinctrl_mipi_ltk0680ytmdb: mipi-ltk0680ytmdbgrp {
		fsl,pins = <
#define GP_MIPI_RESET	<&gpio3 14 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14	0x16
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT		0x16
		>;
	};

	pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
		fsl,pins = <
#define GP_REG_USB_OTG_VBUS	<&gpio1 12 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x16
		>;
	};

	pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
		fsl,pins = <
#define GP_REG_WLAN_VMMC	<&gpio3 20 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20	0x16
		>;
	};

	pinctrl_sai1: sai1grp {
		fsl,pins = <
			/* wm8960 */
			MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0		0xd6
			MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0		0xd6
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			/* Bluetooth PCM */
			MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6
			MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0		0xd6
		>;
	};

	pinctrl_sound_wm8960: souncd-wm8960grp {
		fsl,pins = <
#define GPIRQ_MIC_DET		<&gpio5 12 IRQ_TYPE_LEVEL_HIGH>
			MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12		0x01
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x45
			MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX		0x45
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x45
			MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x45
			MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x45
			MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x45
		>;
	};

	pinctrl_usb3_0: usb3-0grp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC		0x16
		>;
	};

	pinctrl_usb3_1: usb3-1grp {
		fsl,pins = <
#define GP_USB3_1_HUB_RESET	<&gpio1 14 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x16
#define GP_USB3_1_DN3_SD_RESET	<&gpio3 17 GPIO_ACTIVE_HIGH>
			MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17		0x61
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xc3
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xc3
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xc3
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xc3
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xc3
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xc3
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
#if 0
			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
#else
#define GP_EMMC_RESET		<&gpio2 10 GPIO_ACTIVE_LOW>
			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
#endif
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x8d
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xcd
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xcd
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xcd
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xcd
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xcd
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xcd
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xcd
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xcd
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xcd
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x9f
			MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD			0xdf
			MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0		0xdf
			MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1		0xdf
			MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2		0xdf
			MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3		0xdf
			MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4		0xdf
			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xdf
			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xdf
			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xdf
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
			/* Bluetooth slow clock */
			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x03
			MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12		0x19	/* J19 pin 9 */
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x8d
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xcd
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xcd
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xcd
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xcd
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xcd
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x9f
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xdf
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xdf
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xdf
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xdf
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xdf
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
		>;
	};
};

/ {
	model = "Boundary Devices i.MX8MQ BIO";
	compatible = "boundary,imx8mq-bio", "fsl,imx8mq";

	chosen {
		bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
#if 0
		stdout-path = &uart1;
#endif
	};

#if 0
	backlight_mipi: backlight-mipi {
		brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
		compatible = "pwm-backlight";
		default-brightness-level = <8>;
		display = <&lcdif>;
		pwms = <&pwm3 0 30000>;		/* 33.3 Khz */
		status = "disabled";
	};
#endif

	bt-rfkill {
		compatible = "net,rfkill-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_bt_rfkill>;
		name = "bt-rfkill";
		type = <2>; /* Bluetooth */
		reset-gpios = GP_BT_RFKILL_RESET;
		status = "okay";
	};

	gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_keys>;

		power {
			label = "Power Button";
			gpios = GP_GPIOKEY_POWER;
			linux,code = <KEY_POWER>;
			gpio-key,wakeup;
		};

		j1-p2 {
			label = "j1-p2";
			gpios = GP_GPIOKEY_J1_P2;
			linux,code = <KEY_2>;
		};

		j1-p3 {
			label = "j1-p3";
			gpios = GP_GPIOKEY_J1_P3;
			linux,code = <KEY_3>;
		};

		j1-p4 {
			label = "j1-p4";
			gpios = GP_GPIOKEY_J1_P4;
			linux,code = <KEY_4>;
		};

		j1-p5 {
			label = "j1-p5";
			gpios = GP_GPIOKEY_J1_P5;
			linux,code = <KEY_5>;
		};

		j1-p6 {
			label = "j1-p6";
			gpios = GP_GPIOKEY_J1_P6;
			linux,code = <KEY_6>;
		};

		j1-p7 {
			label = "j1-p7";
			gpios = GP_GPIOKEY_J1_P7;
			linux,code = <KEY_7>;
		};

		j1-p8 {
			label = "j1-p8";
			gpios = GP_GPIOKEY_J1_P8;
			linux,code = <KEY_8>;
		};

		j1-p9 {
			label = "j1-p9";
			gpios = GP_GPIOKEY_J1_P9;
			linux,code = <KEY_9>;
		};

		j17-p2 {
			label = "j17-p2";
			gpios = GP_GPIOKEY_J17_P2;
			linux,code = <KEY_F2>;
		};

		j17-p3 {
			label = "j17-p3";
			gpios = GP_GPIOKEY_J17_P3;
			linux,code = <KEY_F3>;
		};

		j17-p4 {
			label = "j17-p4";
			gpios = GP_GPIOKEY_J17_P4;
			linux,code = <KEY_F4>;
		};

		j17-p5 {
			label = "j17-p5";
			gpios = GP_GPIOKEY_J17_P5;
			linux,code = <KEY_F5>;
		};

		j17-p6 {
			label = "j17-p6";
			gpios = GP_GPIOKEY_J17_P6;
			linux,code = <KEY_F6>;
		};

		j21-p2 {
			label = "j21-p2";
			gpios = GP_GPIOKEY_J21_P2;
			linux,code = <KEY_B>;
		};

		j21-p3 {
			label = "j21-p3";
			gpios = GP_GPIOKEY_J21_P3;
			linux,code = <KEY_C>;
		};

		j21-p4 {
			label = "j21-p4";
			gpios = GP_GPIOKEY_J21_P4;
			linux,code = <KEY_D>;
		};

		j21-p5 {
			label = "j21-p5";
			gpios = GP_GPIOKEY_J21_P5;
			linux,code = <KEY_E>;
		};

		j21-p6 {
			label = "j21-p6";
			gpios = GP_GPIOKEY_J21_P6;
			linux,code = <KEY_F>;
		};

		j21-p7 {
			label = "j21-p7";
			gpios = GP_GPIOKEY_J21_P7;
			linux,code = <KEY_G>;
		};

		j21-p8 {
			label = "j21-p8";
			gpios = GP_GPIOKEY_J21_P8;
			linux,code = <KEY_H>;
		};

		j21-p9 {
			label = "j21-p9";
			gpios = GP_GPIOKEY_J21_P9;
			linux,code = <KEY_I>;
		};

		j21-p10 {
			label = "j21-p10";
			gpios = GP_GPIOKEY_J21_P10;
			linux,code = <KEY_J>;
		};
	};

	mipi_mclk: mipi-mclk {
		compatible = "pwm-clock";
		#clock-cells = <0>;
		clock-frequency = <22000000>;
		clock-output-names = "mipi_mclk";
#if 0
		pwms = <&pwm1 0 45>; /* 1 / 45 ns = 22 MHz */
#endif
	};

	reg_usb_otg_vbus: regulator-usb-otg-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
		regulator-name = "usb_otg_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio = GP_REG_USB_OTG_VBUS;
		enable-active-high;
	};

	reg_vref_0v9: regulator-vref-0v9 {
		compatible = "regulator-fixed";
		regulator-name = "vref-0v9";
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;
	};

	reg_vref_1v8: regulator-vref-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vref-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_vref_2v5: regulator-vref-2v5 {
		compatible = "regulator-fixed";
		regulator-name = "vref-2v5";
		regulator-min-microvolt = <2500000>;
		regulator-max-microvolt = <2500000>;
	};

	reg_vref_3v3: regulator-vref-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vref-3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_vref_5v: regulator-vref-5v {
		compatible = "regulator-fixed";
		regulator-name = "vref-5v";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_wlan_vmmc: regulator-wlan-vmmc {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
		regulator-name = "reg_wlan_vmmc";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = GP_REG_WLAN_VMMC;
		startup-delay-us = <70000>;
		enable-active-high;
	};

#if 0
	sound-wm8960 {
		compatible = "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		cpu-dai = <&sai1>;
		codec-master;
		audio-codec = <&wm8960>;
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT1", "Main MIC",
			"Main MIC", "MICB";
		/* JD2: hp detect high for headphone*/
		hp-det = <2 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sound_wm8960>;
	};

	sound_hdmi: sound-hdmi {
		compatible = "fsl,imx-audio-cdnhdmi";
		model = "imx-audio-hdmi";
		audio-cpu = <&sai4>;
		constraint-rate = <32000 44100 48000 96000 192000>;
		protocol = <1>;
		status = HDMI_STATUS;
	};
#endif
};

&A53_0 {
	operating-points = <
		/* kHz    uV */
		1500000 1000000
		1300000 1000000
		1000000 900000
		800000  900000
	>;
};

&clk {
	assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
	assigned-clock-rates = <786432000>, <722534400>;
};

#if 0
&csi1_bridge {
	fsl,mipi-mode;
	fsl,two-8bit-sensor-mode;
	status = "okay";

	port {
		csi1_ep: endpoint {
			remote-endpoint = <&csi1_mipi_ep>;
		};
	};
};

&dcss {
#ifdef MIPI_ON_DCSS
	status = MIPI_DSI_STATUS;
	disp-dev = "mipi_disp";

	clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
		 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
		 <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
		 <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
		 <&clk IMX8MQ_CLK_DUMMY>,
		 <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
	clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";

	assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
			  <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
			  <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
			  <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
			  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
			  <&clk IMX8MQ_VIDEO_PLL1>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_SYS1_PLL_800M>,
				 <&clk IMX8MQ_SYS1_PLL_800M>,
				 <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_CLK_25M>;
	assigned-clock-rates = <600000000>,
			       <800000000>,
			       <400000000>,
			       <400000000>,
			       <0>,
			       <599999999>;

	dcss_disp0: port@0 {
		reg = <0>;

		dcss_disp0_mipi_dsi: mipi_dsi {
			remote-endpoint = <&mipi_dsi_in>;
		};
	};
#else
	status = HDMI_STATUS;
	disp-dev = "hdmi_disp";
#endif
};

#endif

#if 0
&gpu {
	status = "okay";
};

&hdmi {
	assigned-clocks = <&clk IMX8MQ_CLK_CLK2>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_27M>;
	clocks = <&clk IMX8MQ_CLK_CLK2_CG>;
	clock-names = "refclk";
	status = HDMI_STATUS;
};

&hdmi_cec {
	status = HDMI_STATUS;
};
#endif

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

#if 0
	mipi_to_lvds: mipi-to-lvds@2c {
		clocks = <&mipi_dsi_phy 0>;
		clock-names = "mipi_clk";
		compatible = "ti,sn65dsi83";
		display = <&lcdif>;
		display-dsi = <&fb_mipi>;
		enable-gpios = GP_I2C2_SN65DSI83_EN;
		interrupts-extended = GPIRQ_I2C2_SN65DSI83;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2_sn65dsi83>;
		reg = <0x2c>;
		status = "disabled";
	};
#endif

#if 0
	ov5640-mipi1@3c {
		compatible = "ov5640_mipisubdev";
		reg = <0x3c>;
		status = "okay";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2_csi1>;
		clocks = <&clk IMX8MQ_CLK_CLKO2>;
		clock-names = "csi_mclk";
		assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
		assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
		assigned-clock-rates = <25000000>;
		csi_id = <0>;
		AVDD-supply = <&reg_vref_2v5>;
		DVDD-supply = <&reg_vref_3v3>;
		DOVDD-supply = <&reg_vref_1v8>;
		pwn-gpios = GP_CSI1_MIPI_PWDN;
		rst-gpios = GP_CSI1_MIPI_RESET;
		mclk = <25000000>;
		mipi_csi;

		port {
			ov5640_mipi1_ep: endpoint {
				remote-endpoint = <&mipi1_sensor_ep>;
			};
		};
	};
#endif
};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	rtc@68 {
		compatible = "microcrystal,rv4162";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c3_rv4162>;
		reg = <0x68>;
		interrupts-extended = GPIRQ_RV4162;
		wakeup-source;
	};
};

&i2c4 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	status = "okay";

	i2cmux@70 {
		compatible = "pca9540";
		reg = <0x70>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c4a: i2c4@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c4b: i2c4@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	touchscreen@14 {
		compatible = "goodix,gt9271";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c4_gt911>;
		reg = <0x14>;
		esd-recovery-timeout-ms = <2000>;
		interrupts-extended = GPIRQ_GT911;
		irq-gpios = GP_GT911_IRQ;
		reset-gpios = GP_GT911_RESET;
	};

	wm8960: codec@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
		clock-names = "mclk";
		wlf,shared-lrclk;
	};

	touchscreen@38 {
		compatible = "ft5x06-ts";
		interrupts-extended = GPIRQ_I2C4_FT5X06;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c4_ft5x06>;
		reg = <0x38>;
		wakeup-gpios = GP_I2C4_FT5X06_WAKE;
		reset-gpios = GP_I2C4_FT5X06_RESET;
	};

	touchscreen@55 {
		compatible = "sitronix,st1633i";
		reg = <0x55>;
		interrupts-extended = GPIRQ_ST1633;
		/* pins used by touchscreen */
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c4_st1633>;
		reset-gpios = GP_ST1633_RESET;

		wakeup-gpios = GP_ST1633_IRQ;
	};
};

&lcdif {
#if 0
#ifndef MIPI_ON_DCSS
	status = "okay";

	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
			  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
	assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_CLK_25M>;
	max-res = <1920>, <1920>;

	port@0 {
		lcdif_mipi_dsi: mipi-dsi-endpoint {
			remote-endpoint = <&mipi_dsi_in>;
		};
	};
#endif
#endif
};

#if 0
&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	port {
		mipi1_sensor_ep: endpoint1 {
			remote-endpoint = <&ov5640_mipi1_ep>;
			data-lanes = <1 2>;
		};

		csi1_mipi_ep: endpoint2 {
			remote-endpoint = <&csi1_ep>;
		};
	};
};

&mipi_dsi_phy {
	status = MIPI_DSI_STATUS;
};

&mipi_dsi {
	/delete-property/ no_clk_reset;
	status = MIPI_DSI_STATUS;
#ifndef MIPI_ON_DCSS
	as_bridge;
#endif
	assigned-clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
			  <&clk IMX8MQ_CLK_DSI_PHY_REF>,
			  <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
				 <&clk IMX8MQ_VIDEO_PLL1_OUT>,
				 <&clk IMX8MQ_CLK_25M>;
	assigned-clock-rates = <266000000>;

	port@1 {
		mipi_dsi_in: endpoint {
#ifdef MIPI_ON_DCSS
			remote-endpoint = <&dcss_disp0_mipi_dsi>;
#else
			remote-endpoint = <&lcdif_mipi_dsi>;
#endif
		};
	};
};

&mipi_dsi_bridge {
	/delete-property/ no_clk_reset;
	status = MIPI_DSI_STATUS;

	fb_mipi: panel@0 {
		bits-per-color = <8>;
		bridge-de-active = <0>;
#if 0
		bridge-sync-active = <1>;
#endif
		bus-format = "rgb888";
		compatible = "panel,simple";
		delay-power-up = <2>;