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/*
* Copyright (C) 2017 Boundary Devices, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Hynix H5TC4G63CFR-PBA */
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* calibration data (1 board) */
/*
MPDGCTRL0 PHY0 (0x021b083c) = 0x414C014C
MPRDDLCTL PHY0 (0x021b0848) = 0x40403232
MPWRDLCTL PHY0 (0x021b0850) = 0x40403A36
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00000000
*/
#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x414C014C
#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x40403232
#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x40403A36
#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x00000000
#define WALAT 0
/* Enable all clocks */
DATA 4 CCM_CCGR0 0xffffffff
DATA 4 CCM_CCGR1 0xffffffff
DATA 4 CCM_CCGR2 0xffffffff
DATA 4 CCM_CCGR3 0xffffffff
DATA 4 CCM_CCGR4 0xffffffff
DATA 4 CCM_CCGR5 0xffffffff
DATA 4 CCM_CCGR6 0xffffffff
#define RANK 0
#define BUS_WIDTH 16
/* H5TC8G63AMR-PBA */
#if 1
#include "../common/mx6/ddr-setup.cfg"
#else
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
DATA 4, MX6_IOM_DRAM_RESET, 0x000C0030
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
/* Read data DQ Byte0-3 delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
/*
* MDMISC mirroring-off interleaved (row/bank/col)
*/
DATA 4, MX6_MMDC_P0_MDMISC, 0x00201740
/*
* MDSCR con_req
*/
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
#endif
#if 1
#include "../common/mx6/800mhz_256mx16-hynix.cfg"
#else
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
DATA 4, 0x021B082C, 0xf3333333
DATA 4, 0x021B0830, 0xf3333333
DATA 4, 0x021B08C0, 0x00944009
DATA 4, 0x021B0890, 0x00400000
DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B52F3
DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66D0B63
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00000004
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x41640158
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40403237
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x40403C33
DATA 4, MX6_MMDC_P0_MDOTC, 0x1B333030
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
DATA 4, MX6_MMDC_P0_MDASP, 0x0000004F
DATA 4, MX6_MMDC_P0_MDCTL, 0x84180000
DATA 4, MX6_MMDC_P0_MDSCR, 0x02008032
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
DATA 4, MX6_MMDC_P0_MDSCR, 0x15208030
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
DATA 4, MX6_MMDC_P0_MDREF, 0x00000800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000227
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
#endif