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/*
* Copyright (C) 2017 Boundary Devices, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* MT41K128M16JT-125 IT:K */
#define __ASSEMBLY__
#include <config.h>
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/crm_regs.h"
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi/sd/nand/onenand, qspi/nor
*/
BOOT_FROM spi
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* enable cko1 as 32k for slow clock */
DATA 4, CCM_CCOSR, 0x0000008e
/* Enable all clocks */
DATA 4, CCM_CCGR0, 0xffffffff
DATA 4, CCM_CCGR1, 0xffffffff
DATA 4, CCM_CCGR2, 0xffffffff
DATA 4, CCM_CCGR3, 0xffffffff
DATA 4, CCM_CCGR4, 0xffffffff
DATA 4, CCM_CCGR5, 0xffffffff
DATA 4, CCM_CCGR6, 0xffffffff
DATA 4, CCM_CCGR7, 0xffffffff
/* IOMUX - DDR IO Type */
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
/* Clock */
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
/* Address */
DATA 4, MX6_IOM_DRAM_CAS, 0x00000020
DATA 4, MX6_IOM_DRAM_RAS, 0x00000020
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000020
/* Control */
DATA 4, MX6_IOM_DRAM_RESET, 0x00000020
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000020
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000020
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000020
/* Data Strobe */
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
/* Data */
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
/* Calibrations - ZQ */
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
/*
* Calibration settings - 4 board sample
* 00:19:b8:03:11:24
* 00:19:b8:03:17:2a
* 00:19:b8:03:17:2c
* 00:19:b8:03:17:2e
*/
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x41400133
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x01310126
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x42434547
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38383b36
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001c0019
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0016000f
/* Read data bit delay */
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
/* Complete calibration by forced measurement */
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
/*
* Initialize MT41K128M16HA-125
* 14 row + 3 bank + 10 col + 0 rank + 2 width = 29 = 512 MB
* tRCD 13125 ps
* tRP 13125 ps
* tCL 13125 ps
* 396M DDR clock = .396G = 2525.2ps/clocks
* 13125ps / 2525.2ps/clocks = 5.198 clocks
*/
/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
/*
* tRFC:0x3f: 64(0x40) clocks (160000/2525.2)
* tXS:0x43: 68(0x44) clocks (170000/2525.2)
* tXP:b'010': 3 clocks (7500/2525.2)
* tXPDLL:b'1001': 10(0xa) clocks (24000/2525.2)
* tFAW:b'01010': 11(0x0b) clocks (27000/2525.2)
* tCL:b'0011': 6 clocks (13125/2525.2)
*/
DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f4352a3
/*
* tRCD:b'101': 6 clocks (13125/2525.2)
* tRP:b'101': 6 clocks (13125/2525.2)
* tRC:b'10100': 21(0x15) clocks (50625/2525.2)
* tRAS:b'01110': 15(0x0f) clocks (37500/2525.2)
* tRPA:b'1': 7 clocks (tRP[+1]) 6
* b'000'
* tWR:b'101': 6 clocks (15000/2525.2)
* tMRD:b'1011': 12(0xc) clocks (min 4 clocks)4
* b'00'
* tCWL:b'011': 5 clocks (tCL-1)
*/
DATA 4, MX6_MMDC_P0_MDCFG1, 0xb68e8b63
/*
* b'0000000'
* tDLLK:0x1ff(9 bits), 512(0x200) clocks (Jedec for DDR3)
* b'0000000'
* tRTP:b'011': 4 clocks (7500/2525.2), min 4
* tWTR:same bank b'011': 4 clocks (7500/2525.2), min 4
* tRRD:b'011': 4 clocks (5000/2525.2), min 4
*/
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
/*
* RTW_SAME: 2 cycles,
* WTR_DIFF: 3 cycles,
* WTW_DIFF: 3 cycles,
* RTW_DIFF: 2 cycles,
* RTR_DIFF: 2 cycles
*/
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
/*
* tXPR:0x43: 68(0x44) cycles, (170000/2525.2), min 5
* SDE_to_RST:0x10: 14 cycles, (Jedec)
* RST_to_CKE:0x23: 33 cycles (Jedec)
*/
DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
/* end of CS0 US 0xa0000000-1 */
DATA 4, MX6_MMDC_P0_MDASP, 0x0000004f
/* row:14 bits */
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 /* MR2 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 /* MR3 */
DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 /* MR1 */
/*
* b'1' - dll on
* b'010' - tWR 6 clocks
* b'1' - dll reset
* b'0'
* b'01000' - CAS 6
* b'00' Fixed BC4
*/
DATA 4, MX6_MMDC_P0_MDSCR, 0x15208030 /* MR0 */
/* DDR device ZQ calibration */
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
/* Final DDR setup, before operation start */
/*
* Need 8192 cycles in 64ms, or 128K/sec, 4/ sec/32k
* b'01' - 32 Khz
* b'011' - 4 refreshes
*/
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000