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bl = 1;
break;
}
sdmode = (0
| ((dll_on & 0x1) << 12)
| ((wr & 0x7) << 9)
| ((dll_rst & 0x1) << 8)
| ((mode & 0x1) << 7)
| (((caslat >> 1) & 0x7) << 4)
| ((bt & 0x1) << 3)
| ((caslat & 1) << 2)
| ((bl & 0x3) << 0)
);
ddr->ddr_sdram_mode = (0
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
if (unq_mrs_en) { /* unique mode registers are supported */
for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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if (popts->rtt_override)
rtt = popts->rtt_override_value;
else
rtt = popts->cs_local_opts[i].odt_rtt_norm;
esdmode &= 0xFDBB; /* clear bit 9,6,2 */
esdmode |= (0
| ((rtt & 0x4) << 7) /* rtt field is split */
| ((rtt & 0x2) << 5) /* rtt field is split */
| ((rtt & 0x1) << 2) /* rtt field is split */
);
switch (i) {
case 1:
ddr->ddr_sdram_mode_3 = (0
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
break;
case 2:
ddr->ddr_sdram_mode_5 = (0
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
break;
case 3:
ddr->ddr_sdram_mode_7 = (0
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
break;
}
}
debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
ddr->ddr_sdram_mode_3);
debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
ddr->ddr_sdram_mode_5);
debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
ddr->ddr_sdram_mode_5);
}
#else /* !CONFIG_SYS_FSL_DDR3 */
/* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts,
const common_timing_params_t *common_dimm,
unsigned int cas_latency,
unsigned int additive_latency,
const unsigned int unq_mrs_en)
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{
unsigned short esdmode; /* Extended SDRAM mode */
unsigned short sdmode; /* SDRAM mode */
/*
* FIXME: This ought to be pre-calculated in a
* technology-specific routine,
* e.g. compute_DDR2_mode_register(), and then the
* sdmode and esdmode passed in as part of common_dimm.
*/
/* Extended Mode Register */
unsigned int mrs = 0; /* Mode Register Set */
unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
unsigned int ocd = 0; /* 0x0=OCD not supported,
0x7=OCD default state */
unsigned int rtt;
unsigned int al; /* Posted CAS# additive latency (AL) */
unsigned int ods = 0; /* Output Drive Strength:
0 = Full strength (18ohm)
1 = Reduced strength (4ohm) */
unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
1=Disable (Test/Debug) */
/* Mode Register (MR) */
unsigned int mr; /* Mode Register Definition */
unsigned int pd; /* Power-Down Mode */
unsigned int wr; /* Write Recovery */
unsigned int dll_res; /* DLL Reset */
unsigned int mode; /* Normal=0 or Test=1 */
unsigned int caslat = 0;/* CAS# latency */
/* BT: Burst Type (0=Sequential, 1=Interleaved) */
unsigned int bt;
unsigned int bl; /* BL: Burst Length */
#if defined(CONFIG_SYS_FSL_DDR2)
const unsigned int mclk_ps = get_memory_clk_period_ps();
#endif
dqs_en = !popts->dqs_config;
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rtt = fsl_ddr_get_rtt();
al = additive_latency;
esdmode = (0
| ((mrs & 0x3) << 14)
| ((outputs & 0x1) << 12)
| ((rdqs_en & 0x1) << 11)
| ((dqs_en & 0x1) << 10)
| ((ocd & 0x7) << 7)
| ((rtt & 0x2) << 5) /* rtt field is split */
| ((al & 0x7) << 3)
| ((rtt & 0x1) << 2) /* rtt field is split */
| ((ods & 0x1) << 1)
| ((dll_en & 0x1) << 0)
);
mr = 0; /* FIXME: CHECKME */
/*
* 0 = Fast Exit (Normal)
* 1 = Slow Exit (Low Power)
*/
pd = 0;
#if defined(CONFIG_SYS_FSL_DDR1)
wr = 0; /* Historical */
#elif defined(CONFIG_SYS_FSL_DDR2)
wr = (common_dimm->twr_ps + mclk_ps - 1) / mclk_ps - 1;
#endif
dll_res = 0;
mode = 0;
#if defined(CONFIG_SYS_FSL_DDR1)
if (1 <= cas_latency && cas_latency <= 4) {
unsigned char mode_caslat_table[4] = {
0x5, /* 1.5 clocks */
0x2, /* 2.0 clocks */
0x6, /* 2.5 clocks */
0x3 /* 3.0 clocks */
};
caslat = mode_caslat_table[cas_latency - 1];
} else {
printf("Warning: unknown cas_latency %d\n", cas_latency);
#elif defined(CONFIG_SYS_FSL_DDR2)
caslat = cas_latency;
#endif
bt = 0;
switch (popts->burst_length) {
bl = 2;
break;
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bl = 3;
break;
default:
printf("Error: invalid burst length of %u specified. "
" Defaulting to 4 beats.\n",
popts->burst_length);
bl = 2;
break;
}
sdmode = (0
| ((mr & 0x3) << 14)
| ((pd & 0x1) << 12)
| ((wr & 0x7) << 9)
| ((dll_res & 0x1) << 8)
| ((mode & 0x1) << 7)
| ((caslat & 0x7) << 4)
| ((bt & 0x1) << 3)
| ((bl & 0x7) << 0)
);
ddr->ddr_sdram_mode = (0
| ((esdmode & 0xFFFF) << 16)
| ((sdmode & 0xFFFF) << 0)
);
debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
/* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
{
unsigned int init_value; /* Initialization value */
#ifdef CONFIG_MEM_INIT_VALUE
init_value = CONFIG_MEM_INIT_VALUE;
#else
init_value = 0xDEADBEEF;
ddr->ddr_data_init = init_value;
}
/*
* DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
* The old controller on the 8540/60 doesn't have this register.
* Hope it's OK to set it (to 0) anyway.
*/
static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
unsigned int clk_adjust; /* Clock adjust */
clk_adjust = popts->clk_adjust;
ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
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}
/* DDR Initialization Address (DDR_INIT_ADDR) */
static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
{
unsigned int init_addr = 0; /* Initialization address */
ddr->ddr_init_addr = init_addr;
}
/* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
{
unsigned int uia = 0; /* Use initialization address */
unsigned int init_ext_addr = 0; /* Initialization address */
ddr->ddr_init_ext_addr = (0
| ((uia & 0x1) << 31)
| (init_ext_addr & 0xF)
);
}
/* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
const memctl_options_t *popts)
{
unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
#if defined(CONFIG_SYS_FSL_DDR3)
if (popts->burst_length == DDR_BL8) {
/* We set BL/2 for fixed BL8 */
rrt = 0; /* BL/2 clocks */
wwt = 0; /* BL/2 clocks */
} else {
/* We need to set BL/2 + 2 to BC4 and OTF */
rrt = 2; /* BL/2 + 2 clocks */
wwt = 2; /* BL/2 + 2 clocks */
}
dll_lock = 1; /* tDLLK = 512 clocks from spec */
#endif
ddr->timing_cfg_4 = (0
| ((rwt & 0xf) << 28)
| ((wrt & 0xf) << 24)
| ((rrt & 0xf) << 20)
| ((wwt & 0xf) << 16)
| (dll_lock & 0x3)
);
debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
}
/* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
{
unsigned int rodt_on = 0; /* Read to ODT on */
unsigned int rodt_off = 0; /* Read to ODT off */
unsigned int wodt_on = 0; /* Write to ODT on */
unsigned int wodt_off = 0; /* Write to ODT off */
#if defined(CONFIG_SYS_FSL_DDR3)
/* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
rodt_on = cas_latency - ((ddr->timing_cfg_2 & 0x00780000) >> 19) + 1;
wodt_off = 4; /* 4 clocks */
#endif
ddr->timing_cfg_5 = (0
| ((rodt_on & 0x1f) << 24)
| ((rodt_off & 0x7) << 20)
| ((wodt_on & 0x1f) << 12)
| ((wodt_off & 0x7) << 8)
debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
}
/* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
{
unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
/* Normal Operation Full Calibration Time (tZQoper) */
unsigned int zqoper = 0;
/* Normal Operation Short Calibration Time (tZQCS) */
unsigned int zqcs = 0;
if (zq_en) {
zqinit = 9; /* 512 clocks */
zqoper = 8; /* 256 clocks */
zqcs = 6; /* 64 clocks */
}
ddr->ddr_zq_cntl = (0
| ((zq_en & 0x1) << 31)
| ((zqinit & 0xF) << 24)
| ((zqoper & 0xF) << 16)
| ((zqcs & 0xF) << 8)
);
debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
}
/* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
const memctl_options_t *popts)
{
/*
* First DQS pulse rising edge after margining mode
* is programmed (tWL_MRD)
*/
unsigned int wrlvl_mrd = 0;
/* ODT delay after margining mode is programmed (tWL_ODTEN) */
unsigned int wrlvl_odten = 0;
/* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
unsigned int wrlvl_dqsen = 0;
/* WRLVL_SMPL: Write leveling sample time */
unsigned int wrlvl_smpl = 0;
/* WRLVL_WLR: Write leveling repeition time */
unsigned int wrlvl_wlr = 0;
/* WRLVL_START: Write leveling start time */
unsigned int wrlvl_start = 0;
/* suggest enable write leveling for DDR3 due to fly-by topology */
if (wrlvl_en) {
/* tWL_MRD min = 40 nCK, we set it 64 */
wrlvl_mrd = 0x6;
/* tWL_ODTEN 128 */
wrlvl_odten = 0x7;
/* tWL_DQSEN min = 25 nCK, we set it 32 */
wrlvl_dqsen = 0x5;
/*
* Write leveling sample time at least need 6 clocks
* higher than tWLO to allow enough time for progagation
* delay and sampling the prime data bits.
*/
wrlvl_smpl = 0xf;
/*
* Write leveling repetition time
* at least tWLO + 6 clocks clocks
/*
* Write leveling start time
* The value use for the DQS_ADJUST for the first sample
* when write leveling is enabled. It probably needs to be
* overriden per platform.
/*
* Override the write leveling sample and start time
* according to specific board
*/
if (popts->wrlvl_override) {
wrlvl_smpl = popts->wrlvl_sample;
wrlvl_start = popts->wrlvl_start;
}
ddr->ddr_wrlvl_cntl = (0
| ((wrlvl_en & 0x1) << 31)
| ((wrlvl_mrd & 0x7) << 24)
| ((wrlvl_odten & 0x7) << 20)
| ((wrlvl_dqsen & 0x7) << 16)
| ((wrlvl_smpl & 0xf) << 12)
| ((wrlvl_wlr & 0x7) << 8)
| ((wrlvl_start & 0x1F) << 0)
debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
}
/* DDR Self Refresh Counter (DDR_SR_CNTR) */
static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
/* Self Refresh Idle Threshold */
ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
}
static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
{
if (popts->addr_hash) {
ddr->ddr_eor = 0x40000000; /* address hash enable */
puts("Address hashing enabled.\n");
static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
{
ddr->ddr_cdr1 = popts->ddr_cdr1;
debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
}
static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
{
ddr->ddr_cdr2 = popts->ddr_cdr2;
debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
}
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unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
{
unsigned int res = 0;
/*
* Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
* not set at the same time.
*/
if (ddr->ddr_sdram_cfg & 0x10000000
&& ddr->ddr_sdram_cfg & 0x00008000) {
printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
" should not be set at the same time.\n");
res++;
}
return res;
}
unsigned int
compute_fsl_memctl_config_regs(const memctl_options_t *popts,
fsl_ddr_cfg_regs_t *ddr,
const common_timing_params_t *common_dimm,
const dimm_params_t *dimm_params,
unsigned int dbw_cap_adj,
unsigned int size_only)
{
unsigned int i;
unsigned int cas_latency;
unsigned int additive_latency;
unsigned int sr_it;
unsigned int zq_en;
unsigned int wrlvl_en;
unsigned int ip_rev = 0;
unsigned int unq_mrs_en = 0;
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memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
if (common_dimm == NULL) {
printf("Error: subset DIMM params struct null pointer\n");
return 1;
}
/*
* Process overrides first.
*
* FIXME: somehow add dereated caslat to this
*/
cas_latency = (popts->cas_latency_override)
? popts->cas_latency_override_value
: common_dimm->lowest_common_SPD_caslat;
additive_latency = (popts->additive_latency_override)
? popts->additive_latency_override_value
: common_dimm->additive_latency;
sr_it = (popts->auto_self_refresh_en)
? popts->sr_it
: 0;
/* ZQ calibration */
zq_en = (popts->zq_en) ? 1 : 0;
/* write leveling */
wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
/* Chip Select Memory Bounds (CSn_BNDS) */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
unsigned long long ea, sa;
unsigned int cs_per_dimm
= CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
unsigned int dimm_number
= i / cs_per_dimm;
unsigned long long rank_density
= dimm_params[dimm_number].rank_density >> dbw_cap_adj;
if (dimm_params[dimm_number].n_ranks == 0) {
debug("Skipping setup of CS%u "
"because n_ranks on DIMM %u is 0\n", i, dimm_number);
continue;
}
if (popts->memctl_interleaving) {
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
break;
case FSL_DDR_CS0_CS1:
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
if (i > 1)
cs_en = 0;
break;
case FSL_DDR_CS2_CS3:
if (i > 0)
cs_en = 0;
break;
}
sa = common_dimm->base_address;
ea = sa + common_dimm->total_mem - 1;
} else if (!popts->memctl_interleaving) {
/*
* If memory interleaving between controllers is NOT
* enabled, the starting address for each memory
* controller is distinct. However, because rank
* interleaving is enabled, the starting and ending
* addresses of the total memory on that memory
* controller needs to be programmed into its
* respective CS0_BNDS.
*/
switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
case FSL_DDR_CS0_CS1_CS2_CS3:
sa = common_dimm->base_address;
ea = sa + common_dimm->total_mem - 1;
break;
case FSL_DDR_CS0_CS1_AND_CS2_CS3:
if ((i >= 2) && (dimm_number == 0)) {
sa = dimm_params[dimm_number].base_address +
2 * rank_density;
ea = sa + 2 * rank_density - 1;
} else {
sa = dimm_params[dimm_number].base_address;
ea = sa + 2 * rank_density - 1;
}
break;
case FSL_DDR_CS0_CS1:
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa = dimm_params[dimm_number].base_address;
ea = sa + rank_density - 1;
if (i != 1)
sa += (i % cs_per_dimm) * rank_density;
ea += (i % cs_per_dimm) * rank_density;
} else {
sa = 0;
ea = 0;
}
if (i == 0)
ea += rank_density;
break;
case FSL_DDR_CS2_CS3:
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa = dimm_params[dimm_number].base_address;
ea = sa + rank_density - 1;
if (i != 3)
sa += (i % cs_per_dimm) * rank_density;
ea += (i % cs_per_dimm) * rank_density;
} else {
sa = 0;
ea = 0;
if (i == 2)
ea += (rank_density >> dbw_cap_adj);
break;
default: /* No bank(chip-select) interleaving */
sa = dimm_params[dimm_number].base_address;
ea = sa + rank_density - 1;
if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
sa += (i % cs_per_dimm) * rank_density;
ea += (i % cs_per_dimm) * rank_density;
} else {
sa = 0;
ea = 0;
}
}
sa >>= 24;
ea >>= 24;
if (cs_en) {
ddr->cs[i].bnds = (0
| ((sa & 0xffff) << 16) /* starting address */
| ((ea & 0xffff) << 0) /* ending address */
);
} else {
/* setting bnds to 0xffffffff for inactive CS */
ddr->cs[i].bnds = 0xffffffff;
}
debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
set_csn_config(dimm_number, i, ddr, popts, dimm_params);
set_csn_config_2(i, ddr);
/*
* In the case we only need to compute the ddr sdram size, we only need
* to set csn registers, so return from here.
*/
if (size_only)
return 0;
set_ddr_eor(ddr, popts);
#if !defined(CONFIG_SYS_FSL_DDR1)
set_timing_cfg_0(ddr, popts, dimm_params);
set_timing_cfg_3(ddr, popts, common_dimm, cas_latency,
additive_latency);
set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
set_timing_cfg_2(ddr, popts, common_dimm,
cas_latency, additive_latency);
set_ddr_cdr1(ddr, popts);
set_ddr_sdram_cfg(ddr, popts, common_dimm);
ip_rev = fsl_ddr_get_version();
if (ip_rev > 0x40400)
unq_mrs_en = 1;
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en);
set_ddr_sdram_interval(ddr, popts, common_dimm);
set_ddr_data_init(ddr);
set_ddr_sdram_clk_cntl(ddr, popts);
set_ddr_init_addr(ddr);
set_ddr_init_ext_addr(ddr);
set_timing_cfg_4(ddr, popts);
set_timing_cfg_5(ddr, cas_latency);
set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
set_ddr_sr_cntr(ddr, sr_it);
set_ddr_sdram_rcw(ddr, popts, common_dimm);
#ifdef CONFIG_SYS_FSL_DDR_EMU
/* disble DDR training for emulator */
ddr->debug[2] = 0x00000400;
ddr->debug[4] = 0xff800000;
#endif
return check_fsl_memctl_config_regs(ddr);
}