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* Copyright 2010-2014 Freescale Semiconductor, Inc.
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
* Based on code from spd_sdram.c
* Author: James Yang [at freescale.com]
* York Sun [at freescale.com]
*/
#include <common.h>
#include <linux/ctype.h>
#include <asm/types.h>
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
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/* Option parameter Structures */
struct options_string {
const char *option_name;
size_t offset;
unsigned int size;
const char printhex;
};
static unsigned int picos_to_mhz(unsigned int picos)
{
return 1000000 / picos;
}
static void print_option_table(const struct options_string *table,
int table_size,
const void *base)
{
unsigned int i;
unsigned int *ptr;
unsigned long long *ptr_l;
for (i = 0; i < table_size; i++) {
switch (table[i].size) {
case 4:
ptr = (unsigned int *) (base + table[i].offset);
if (table[i].printhex) {
printf("%s = 0x%08X\n",
table[i].option_name, *ptr);
} else {
printf("%s = %u\n",
table[i].option_name, *ptr);
}
break;
case 8:
ptr_l = (unsigned long long *) (base + table[i].offset);
printf("%s = %llu\n",
table[i].option_name, *ptr_l);
break;
default:
printf("Unrecognized size!\n");
break;
}
}
}
static int handle_option_table(const struct options_string *table,
int table_size,
void *base,
const char *opt,
const char *val)
{
unsigned int i;
unsigned int value, *ptr;
unsigned long long value_l, *ptr_l;
for (i = 0; i < table_size; i++) {
if (strcmp(table[i].option_name, opt) != 0)
continue;
switch (table[i].size) {
case 4:
value = simple_strtoul(val, NULL, 0);
ptr = base + table[i].offset;
*ptr = value;
break;
case 8:
value_l = simple_strtoull(val, NULL, 0);
ptr_l = base + table[i].offset;
*ptr_l = value_l;
break;
default:
printf("Unrecognized size!\n");
break;
}
return 1;
}
return 0;
}
static void fsl_ddr_generic_edit(void *pdata,
void *pend,
unsigned int element_size,
unsigned int element_num,
unsigned int value)
{
char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
pcdata += element_num * element_size;
if ((pcdata + element_size) > (char *) pend) {
printf("trying to write past end of data\n");
return;
}
switch (element_size) {
case 1:
__raw_writeb(value, pcdata);
break;
case 2:
__raw_writew(value, pcdata);
break;
case 4:
__raw_writel(value, pcdata);
break;
default:
printf("unexpected element size %u\n", element_size);
break;
}
}
static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
unsigned int ctrl_num,
unsigned int dimm_num,
unsigned int element_num,
unsigned int value)
{
generic_spd_eeprom_t *pspd;
pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
}
#define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
sizeof((common_timing_params_t *)0)->x, 0}
static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
unsigned int ctrl_num,
const char *optname_str,
const char *value_str)
{
common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
static const struct options_string options[] = {
COMMON_TIMING(tckmin_x_ps),
COMMON_TIMING(tckmax_ps),
COMMON_TIMING(taamin_ps),
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
#ifdef CONFIG_SYS_FSL_DDR4
COMMON_TIMING(trfc1_ps),
COMMON_TIMING(trfc2_ps),
COMMON_TIMING(trfc4_ps),
COMMON_TIMING(trrds_ps),
COMMON_TIMING(trrdl_ps),
COMMON_TIMING(tccdl_ps),
#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
COMMON_TIMING(trrd_ps),
COMMON_TIMING(trtp_ps),
#endif
COMMON_TIMING(twr_ps),
COMMON_TIMING(trc_ps),
COMMON_TIMING(refresh_rate_ps),
COMMON_TIMING(extended_op_srt),
#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
COMMON_TIMING(tis_ps),
COMMON_TIMING(tih_ps),
COMMON_TIMING(tds_ps),
COMMON_TIMING(tdh_ps),
COMMON_TIMING(tdqsq_max_ps),
COMMON_TIMING(tqhs_ps),
COMMON_TIMING(ndimms_present),
COMMON_TIMING(lowest_common_spd_caslat),
COMMON_TIMING(highest_common_derated_caslat),
COMMON_TIMING(additive_latency),
COMMON_TIMING(all_dimms_burst_lengths_bitmask),
COMMON_TIMING(all_dimms_registered),
COMMON_TIMING(all_dimms_unbuffered),
COMMON_TIMING(all_dimms_ecc_capable),
COMMON_TIMING(total_mem),
COMMON_TIMING(base_address),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
if (handle_option_table(options, n_opts, p, optname_str, value_str))
return;
printf("Error: couldn't find option string %s\n", optname_str);
}
#define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
sizeof((dimm_params_t *)0)->x, 0}
#define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
sizeof((dimm_params_t *)0)->x, 1}
static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
unsigned int ctrl_num,
unsigned int dimm_num,
const char *optname_str,
const char *value_str)
{
dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
static const struct options_string options[] = {
DIMM_PARM(n_ranks),
DIMM_PARM(data_width),
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
DIMM_PARM(edc_config),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(bank_addr_bits),
DIMM_PARM(bank_group_bits),
#else
DIMM_PARM(n_banks_per_sdram_device),
DIMM_PARM(burst_lengths_bitmask),
DIMM_PARM(row_density),
DIMM_PARM(tckmin_x_ps),
DIMM_PARM(tckmin_x_minus_1_ps),
DIMM_PARM(tckmin_x_minus_2_ps),
DIMM_PARM(tckmax_ps),
DIMM_PARM(caslat_x),
DIMM_PARM(caslat_x_minus_1),
DIMM_PARM(caslat_x_minus_2),
DIMM_PARM(caslat_lowest_derated),
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(trfc1_ps),
DIMM_PARM(trfc2_ps),
DIMM_PARM(trfc4_ps),
DIMM_PARM(trrds_ps),
DIMM_PARM(trrdl_ps),
DIMM_PARM(tccdl_ps),
#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(trfc_ps),
DIMM_PARM(trrd_ps),
DIMM_PARM(trtp_ps),
#endif
DIMM_PARM(refresh_rate_ps),
DIMM_PARM(extended_op_srt),
#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
DIMM_PARM(tis_ps),
DIMM_PARM(tih_ps),
DIMM_PARM(tds_ps),
DIMM_PARM(tdh_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM_HEX(dq_mapping[0]),
DIMM_PARM_HEX(dq_mapping[1]),
DIMM_PARM_HEX(dq_mapping[2]),
DIMM_PARM_HEX(dq_mapping[3]),
DIMM_PARM_HEX(dq_mapping[4]),
DIMM_PARM_HEX(dq_mapping[5]),
DIMM_PARM_HEX(dq_mapping[6]),
DIMM_PARM_HEX(dq_mapping[7]),
DIMM_PARM_HEX(dq_mapping[8]),
DIMM_PARM_HEX(dq_mapping[9]),
DIMM_PARM_HEX(dq_mapping[10]),
DIMM_PARM_HEX(dq_mapping[11]),
DIMM_PARM_HEX(dq_mapping[12]),
DIMM_PARM_HEX(dq_mapping[13]),
DIMM_PARM_HEX(dq_mapping[14]),
DIMM_PARM_HEX(dq_mapping[15]),
DIMM_PARM_HEX(dq_mapping[16]),
DIMM_PARM_HEX(dq_mapping[17]),
DIMM_PARM(dq_mapping_ors),
#endif
DIMM_PARM(rank_density),
DIMM_PARM(capacity),
DIMM_PARM(base_address),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
if (handle_option_table(options, n_opts, p, optname_str, value_str))
return;
printf("couldn't find option string %s\n", optname_str);
}
static void print_dimm_parameters(const dimm_params_t *pdimm)
{
static const struct options_string options[] = {
DIMM_PARM(n_ranks),
DIMM_PARM(data_width),
DIMM_PARM(primary_sdram_width),
DIMM_PARM(ec_sdram_width),
DIMM_PARM(registered_dimm),
DIMM_PARM(n_row_addr),
DIMM_PARM(n_col_addr),
DIMM_PARM(edc_config),
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(bank_addr_bits),
DIMM_PARM(bank_group_bits),
#else
DIMM_PARM(n_banks_per_sdram_device),
DIMM_PARM(tckmin_x_ps),
DIMM_PARM(tckmin_x_minus_1_ps),
DIMM_PARM(tckmin_x_minus_2_ps),
DIMM_PARM(tckmax_ps),
DIMM_PARM(caslat_x),
DIMM_PARM(taa_ps),
DIMM_PARM(caslat_x_minus_1),
DIMM_PARM(caslat_x_minus_2),
DIMM_PARM(caslat_lowest_derated),
DIMM_PARM(trcd_ps),
DIMM_PARM(trp_ps),
DIMM_PARM(tras_ps),
#if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
DIMM_PARM(tfaw_ps),
#endif
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM(trfc1_ps),
DIMM_PARM(trfc2_ps),
DIMM_PARM(trfc4_ps),
DIMM_PARM(trrds_ps),
DIMM_PARM(trrdl_ps),
DIMM_PARM(tccdl_ps),
#else
DIMM_PARM(twr_ps),
DIMM_PARM(twtr_ps),
DIMM_PARM(trfc_ps),
DIMM_PARM(trrd_ps),
DIMM_PARM(trtp_ps),
#endif
DIMM_PARM(refresh_rate_ps),
#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
DIMM_PARM(tis_ps),
DIMM_PARM(tih_ps),
DIMM_PARM(tds_ps),
DIMM_PARM(tdh_ps),
DIMM_PARM(tdqsq_max_ps),
DIMM_PARM(tqhs_ps),
#endif
#ifdef CONFIG_SYS_FSL_DDR4
DIMM_PARM_HEX(dq_mapping[0]),
DIMM_PARM_HEX(dq_mapping[1]),
DIMM_PARM_HEX(dq_mapping[2]),
DIMM_PARM_HEX(dq_mapping[3]),
DIMM_PARM_HEX(dq_mapping[4]),
DIMM_PARM_HEX(dq_mapping[5]),
DIMM_PARM_HEX(dq_mapping[6]),
DIMM_PARM_HEX(dq_mapping[7]),
DIMM_PARM_HEX(dq_mapping[8]),
DIMM_PARM_HEX(dq_mapping[9]),
DIMM_PARM_HEX(dq_mapping[10]),
DIMM_PARM_HEX(dq_mapping[11]),
DIMM_PARM_HEX(dq_mapping[12]),
DIMM_PARM_HEX(dq_mapping[13]),
DIMM_PARM_HEX(dq_mapping[14]),
DIMM_PARM_HEX(dq_mapping[15]),
DIMM_PARM_HEX(dq_mapping[16]),
DIMM_PARM_HEX(dq_mapping[17]),
DIMM_PARM(dq_mapping_ors),
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};
static const unsigned int n_opts = ARRAY_SIZE(options);
if (pdimm->n_ranks == 0) {
printf("DIMM not present\n");
return;
}
printf("DIMM organization parameters:\n");
printf("module part name = %s\n", pdimm->mpart);
printf("rank_density = %llu bytes (%llu megabytes)\n",
pdimm->rank_density, pdimm->rank_density / 0x100000);
printf("capacity = %llu bytes (%llu megabytes)\n",
pdimm->capacity, pdimm->capacity / 0x100000);
printf("burst_lengths_bitmask = %02X\n",
pdimm->burst_lengths_bitmask);
printf("base_addresss = %llu (%08llX %08llX)\n",
pdimm->base_address,
(pdimm->base_address >> 32),
pdimm->base_address & 0xFFFFFFFF);
print_option_table(options, n_opts, pdimm);
}
static void print_lowest_common_dimm_parameters(
const common_timing_params_t *plcd_dimm_params)
{
static const struct options_string options[] = {
COMMON_TIMING(taamin_ps),
COMMON_TIMING(trcd_ps),
COMMON_TIMING(trp_ps),
COMMON_TIMING(tras_ps),
#ifdef CONFIG_SYS_FSL_DDR4
COMMON_TIMING(trfc1_ps),
COMMON_TIMING(trfc2_ps),
COMMON_TIMING(trfc4_ps),
COMMON_TIMING(trrds_ps),
COMMON_TIMING(trrdl_ps),
COMMON_TIMING(tccdl_ps),
#else
COMMON_TIMING(twtr_ps),
COMMON_TIMING(trfc_ps),
COMMON_TIMING(trrd_ps),
COMMON_TIMING(trtp_ps),
#endif
COMMON_TIMING(twr_ps),
COMMON_TIMING(trc_ps),
COMMON_TIMING(refresh_rate_ps),
COMMON_TIMING(extended_op_srt),
#if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
COMMON_TIMING(tis_ps),
COMMON_TIMING(tih_ps),
COMMON_TIMING(tds_ps),
COMMON_TIMING(tdh_ps),
COMMON_TIMING(tdqsq_max_ps),
COMMON_TIMING(tqhs_ps),
#endif
COMMON_TIMING(lowest_common_spd_caslat),
COMMON_TIMING(highest_common_derated_caslat),
COMMON_TIMING(additive_latency),
COMMON_TIMING(ndimms_present),
COMMON_TIMING(all_dimms_registered),
COMMON_TIMING(all_dimms_unbuffered),
COMMON_TIMING(all_dimms_ecc_capable),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
/* Clock frequencies */
printf("tckmin_x_ps = %u (%u MHz)\n",
plcd_dimm_params->tckmin_x_ps,
picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
printf("tckmax_ps = %u (%u MHz)\n",
plcd_dimm_params->tckmax_ps,
picos_to_mhz(plcd_dimm_params->tckmax_ps));
printf("all_dimms_burst_lengths_bitmask = %02X\n",
plcd_dimm_params->all_dimms_burst_lengths_bitmask);
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print_option_table(options, n_opts, plcd_dimm_params);
printf("total_mem = %llu (%llu megabytes)\n",
plcd_dimm_params->total_mem,
plcd_dimm_params->total_mem / 0x100000);
printf("base_address = %llu (%llu megabytes)\n",
plcd_dimm_params->base_address,
plcd_dimm_params->base_address / 0x100000);
}
#define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
sizeof((memctl_options_t *)0)->x, 0}
#define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
offsetof(memctl_options_t, cs_local_opts[x].y), \
sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
unsigned int ctl_num,
const char *optname_str,
const char *value_str)
{
memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
/*
* This array all on the stack and *computed* each time this
* function is rung.
*/
static const struct options_string options[] = {
CTRL_OPTIONS_CS(0, odt_rd_cfg),
CTRL_OPTIONS_CS(0, odt_wr_cfg),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CTRL_OPTIONS_CS(1, odt_rd_cfg),
CTRL_OPTIONS_CS(1, odt_wr_cfg),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CTRL_OPTIONS_CS(2, odt_rd_cfg),
CTRL_OPTIONS_CS(2, odt_wr_cfg),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CTRL_OPTIONS_CS(3, odt_rd_cfg),
CTRL_OPTIONS_CS(3, odt_wr_cfg),
#endif
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
CTRL_OPTIONS_CS(0, odt_rtt_norm),
CTRL_OPTIONS_CS(0, odt_rtt_wr),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CTRL_OPTIONS_CS(1, odt_rtt_norm),
CTRL_OPTIONS_CS(1, odt_rtt_wr),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CTRL_OPTIONS_CS(2, odt_rtt_norm),
CTRL_OPTIONS_CS(2, odt_rtt_wr),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CTRL_OPTIONS_CS(3, odt_rtt_norm),
CTRL_OPTIONS_CS(3, odt_rtt_wr),
#endif
#endif
CTRL_OPTIONS(memctl_interleaving),
CTRL_OPTIONS(memctl_interleaving_mode),
CTRL_OPTIONS(ba_intlv_ctl),
CTRL_OPTIONS(ecc_mode),
CTRL_OPTIONS(ecc_init_using_memctl),
CTRL_OPTIONS(dqs_config),
CTRL_OPTIONS(self_refresh_in_sleep),
CTRL_OPTIONS(dynamic_power),
CTRL_OPTIONS(data_bus_width),
CTRL_OPTIONS(burst_length),
CTRL_OPTIONS(cas_latency_override),
CTRL_OPTIONS(cas_latency_override_value),
CTRL_OPTIONS(use_derated_caslat),
CTRL_OPTIONS(additive_latency_override),
CTRL_OPTIONS(additive_latency_override_value),
CTRL_OPTIONS(clk_adjust),
CTRL_OPTIONS(cpo_override),
CTRL_OPTIONS(write_data_delay),
CTRL_OPTIONS(half_strength_driver_enable),
/*
* These can probably be changed to 2T_EN and 3T_EN
* (using a leading numerical character) without problem
*/
CTRL_OPTIONS(twot_en),
CTRL_OPTIONS(threet_en),
CTRL_OPTIONS(ap_en),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
CTRL_OPTIONS(ddr_cdr1),
CTRL_OPTIONS(ddr_cdr2),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
CTRL_OPTIONS(rtt_override),
CTRL_OPTIONS(rtt_override_value),
CTRL_OPTIONS(rtt_wr_override_value),
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};
static const unsigned int n_opts = ARRAY_SIZE(options);
if (handle_option_table(options, n_opts, p,
optname_str, value_str))
return;
printf("couldn't find option string %s\n", optname_str);
}
#define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
#define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
{
unsigned int i;
static const struct options_string options[] = {
CFG_REGS_CS(0, bnds),
CFG_REGS_CS(0, config),
CFG_REGS_CS(0, config_2),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CFG_REGS_CS(1, bnds),
CFG_REGS_CS(1, config),
CFG_REGS_CS(1, config_2),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CFG_REGS_CS(2, bnds),
CFG_REGS_CS(2, config),
CFG_REGS_CS(2, config_2),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CFG_REGS_CS(3, bnds),
CFG_REGS_CS(3, config),
CFG_REGS_CS(3, config_2),
#endif
CFG_REGS(timing_cfg_3),
CFG_REGS(timing_cfg_0),
CFG_REGS(timing_cfg_1),
CFG_REGS(timing_cfg_2),
CFG_REGS(ddr_sdram_cfg),
CFG_REGS(ddr_sdram_cfg_2),
CFG_REGS(ddr_sdram_cfg_3),
CFG_REGS(ddr_sdram_mode),
CFG_REGS(ddr_sdram_mode_2),
CFG_REGS(ddr_sdram_mode_3),
CFG_REGS(ddr_sdram_mode_4),
CFG_REGS(ddr_sdram_mode_5),
CFG_REGS(ddr_sdram_mode_6),
CFG_REGS(ddr_sdram_mode_7),
CFG_REGS(ddr_sdram_mode_8),
#ifdef CONFIG_SYS_FSL_DDR4
CFG_REGS(ddr_sdram_mode_9),
CFG_REGS(ddr_sdram_mode_10),
CFG_REGS(ddr_sdram_mode_11),
CFG_REGS(ddr_sdram_mode_12),
CFG_REGS(ddr_sdram_mode_13),
CFG_REGS(ddr_sdram_mode_14),
CFG_REGS(ddr_sdram_mode_15),
CFG_REGS(ddr_sdram_mode_16),
#endif
CFG_REGS(ddr_sdram_interval),
CFG_REGS(ddr_data_init),
CFG_REGS(ddr_sdram_clk_cntl),
CFG_REGS(ddr_init_addr),
CFG_REGS(ddr_init_ext_addr),
CFG_REGS(timing_cfg_4),
CFG_REGS(timing_cfg_5),
#ifdef CONFIG_SYS_FSL_DDR4
CFG_REGS(timing_cfg_6),
CFG_REGS(timing_cfg_7),
CFG_REGS(timing_cfg_8),
CFG_REGS(timing_cfg_9),
#endif
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
CFG_REGS(ddr_wrlvl_cntl_2),
CFG_REGS(ddr_wrlvl_cntl_3),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
CFG_REGS(dq_map_0),
CFG_REGS(dq_map_1),
CFG_REGS(dq_map_2),
CFG_REGS(dq_map_3),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
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};
static const unsigned int n_opts = ARRAY_SIZE(options);
print_option_table(options, n_opts, ddr);
for (i = 0; i < 32; i++)
printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
}
static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
unsigned int ctrl_num,
const char *regname,
const char *value_str)
{
unsigned int i;
fsl_ddr_cfg_regs_t *ddr;
char buf[20];
static const struct options_string options[] = {
CFG_REGS_CS(0, bnds),
CFG_REGS_CS(0, config),
CFG_REGS_CS(0, config_2),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CFG_REGS_CS(1, bnds),
CFG_REGS_CS(1, config),
CFG_REGS_CS(1, config_2),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CFG_REGS_CS(2, bnds),
CFG_REGS_CS(2, config),
CFG_REGS_CS(2, config_2),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
CFG_REGS_CS(3, bnds),
CFG_REGS_CS(3, config),
CFG_REGS_CS(3, config_2),
#endif
CFG_REGS(timing_cfg_3),
CFG_REGS(timing_cfg_0),
CFG_REGS(timing_cfg_1),
CFG_REGS(timing_cfg_2),
CFG_REGS(ddr_sdram_cfg),
CFG_REGS(ddr_sdram_cfg_2),
CFG_REGS(ddr_sdram_cfg_3),
CFG_REGS(ddr_sdram_mode),
CFG_REGS(ddr_sdram_mode_2),
CFG_REGS(ddr_sdram_mode_3),
CFG_REGS(ddr_sdram_mode_4),
CFG_REGS(ddr_sdram_mode_5),
CFG_REGS(ddr_sdram_mode_6),
CFG_REGS(ddr_sdram_mode_7),
CFG_REGS(ddr_sdram_mode_8),
#ifdef CONFIG_SYS_FSL_DDR4
CFG_REGS(ddr_sdram_mode_9),
CFG_REGS(ddr_sdram_mode_10),
CFG_REGS(ddr_sdram_mode_11),
CFG_REGS(ddr_sdram_mode_12),
CFG_REGS(ddr_sdram_mode_13),
CFG_REGS(ddr_sdram_mode_14),
CFG_REGS(ddr_sdram_mode_15),
CFG_REGS(ddr_sdram_mode_16),
#endif
CFG_REGS(ddr_sdram_interval),
CFG_REGS(ddr_data_init),
CFG_REGS(ddr_sdram_clk_cntl),
CFG_REGS(ddr_init_addr),
CFG_REGS(ddr_init_ext_addr),
CFG_REGS(timing_cfg_4),
CFG_REGS(timing_cfg_5),
#ifdef CONFIG_SYS_FSL_DDR4
CFG_REGS(timing_cfg_6),
CFG_REGS(timing_cfg_7),
CFG_REGS(timing_cfg_8),
CFG_REGS(timing_cfg_9),
#endif
CFG_REGS(ddr_zq_cntl),
CFG_REGS(ddr_wrlvl_cntl),
CFG_REGS(ddr_wrlvl_cntl_2),
CFG_REGS(ddr_wrlvl_cntl_3),
CFG_REGS(ddr_sr_cntr),
CFG_REGS(ddr_sdram_rcw_1),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_cdr1),
CFG_REGS(ddr_cdr2),
CFG_REGS(dq_map_0),
CFG_REGS(dq_map_1),
CFG_REGS(dq_map_2),
CFG_REGS(dq_map_3),
CFG_REGS(err_disable),
CFG_REGS(err_int_en),
CFG_REGS(ddr_sdram_rcw_2),
CFG_REGS(ddr_sdram_rcw_2),
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};
static const unsigned int n_opts = ARRAY_SIZE(options);
debug("fsl_ddr_regs_edit: ctrl_num = %u, "
"regname = %s, value = %s\n",
ctrl_num, regname, value_str);
if (ctrl_num > CONFIG_NUM_DDR_CONTROLLERS)
return;
ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
if (handle_option_table(options, n_opts, ddr, regname, value_str))
return;
for (i = 0; i < 32; i++) {
unsigned int value = simple_strtoul(value_str, NULL, 0);
sprintf(buf, "debug_%u", i + 1);
if (strcmp(buf, regname) == 0) {
ddr->debug[i] = value;
return;
}
}
printf("Error: couldn't find register string %s\n", regname);
}
#define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
sizeof((memctl_options_t *)0)->x, 1}
static void print_memctl_options(const memctl_options_t *popts)
{
static const struct options_string options[] = {
CTRL_OPTIONS_CS(0, odt_rd_cfg),
CTRL_OPTIONS_CS(0, odt_wr_cfg),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CTRL_OPTIONS_CS(1, odt_rd_cfg),
CTRL_OPTIONS_CS(1, odt_wr_cfg),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CTRL_OPTIONS_CS(2, odt_rd_cfg),
CTRL_OPTIONS_CS(2, odt_wr_cfg),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
CTRL_OPTIONS_CS(3, odt_rd_cfg),
CTRL_OPTIONS_CS(3, odt_wr_cfg),
#endif
#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
CTRL_OPTIONS_CS(0, odt_rtt_norm),
CTRL_OPTIONS_CS(0, odt_rtt_wr),
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
CTRL_OPTIONS_CS(1, odt_rtt_norm),
CTRL_OPTIONS_CS(1, odt_rtt_wr),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
CTRL_OPTIONS_CS(2, odt_rtt_norm),
CTRL_OPTIONS_CS(2, odt_rtt_wr),
#endif
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
CTRL_OPTIONS_CS(3, odt_rtt_norm),
CTRL_OPTIONS_CS(3, odt_rtt_wr),
#endif
#endif
CTRL_OPTIONS(memctl_interleaving),
CTRL_OPTIONS(memctl_interleaving_mode),
CTRL_OPTIONS_HEX(ba_intlv_ctl),
CTRL_OPTIONS(ecc_mode),
CTRL_OPTIONS(ecc_init_using_memctl),
CTRL_OPTIONS(dqs_config),
CTRL_OPTIONS(self_refresh_in_sleep),
CTRL_OPTIONS(dynamic_power),
CTRL_OPTIONS(data_bus_width),
CTRL_OPTIONS(burst_length),
CTRL_OPTIONS(cas_latency_override),
CTRL_OPTIONS(cas_latency_override_value),
CTRL_OPTIONS(use_derated_caslat),
CTRL_OPTIONS(additive_latency_override),
CTRL_OPTIONS(additive_latency_override_value),
CTRL_OPTIONS(clk_adjust),
CTRL_OPTIONS(cpo_override),
CTRL_OPTIONS(write_data_delay),
CTRL_OPTIONS(half_strength_driver_enable),
/*
* These can probably be changed to 2T_EN and 3T_EN
* (using a leading numerical character) without problem
*/
CTRL_OPTIONS(twot_en),
CTRL_OPTIONS(threet_en),
CTRL_OPTIONS(registered_dimm_en),
CTRL_OPTIONS(mirrored_dimm),
CTRL_OPTIONS(ap_en),
CTRL_OPTIONS(bstopre),
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
CTRL_OPTIONS_HEX(ddr_cdr1),
CTRL_OPTIONS_HEX(ddr_cdr2),
CTRL_OPTIONS(tfaw_window_four_activates_ps),
CTRL_OPTIONS(trwt_override),
CTRL_OPTIONS(trwt),
CTRL_OPTIONS(rtt_override),
CTRL_OPTIONS(rtt_override_value),
CTRL_OPTIONS(rtt_wr_override_value),
};
static const unsigned int n_opts = ARRAY_SIZE(options);
print_option_table(options, n_opts, popts);
}
#ifdef CONFIG_SYS_FSL_DDR1
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void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
{
unsigned int i;
printf("%-3d : %02x %s\n", 0, spd->info_size,
" spd->info_size, * 0 # bytes written into serial memory *");
printf("%-3d : %02x %s\n", 1, spd->chip_size,
" spd->chip_size, * 1 Total # bytes of SPD memory device *");
printf("%-3d : %02x %s\n", 2, spd->mem_type,
" spd->mem_type, * 2 Fundamental memory type *");
printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
" spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
" spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
printf("%-3d : %02x %s\n", 5, spd->nrows,
" spd->nrows * 5 # of DIMM Banks *");
printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
" spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
" spd->dataw_msb, * 7 Data Width msb of this assembly *");
printf("%-3d : %02x %s\n", 8, spd->voltage,
" spd->voltage, * 8 Voltage intf std of this assembly *");
printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
" spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
printf("%-3d : %02x %s\n", 10, spd->clk_access,
" spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
printf("%-3d : %02x %s\n", 11, spd->config,
" spd->config, * 11 DIMM Configuration type *");
printf("%-3d : %02x %s\n", 12, spd->refresh,
" spd->refresh, * 12 Refresh Rate/Type *");
printf("%-3d : %02x %s\n", 13, spd->primw,
" spd->primw, * 13 Primary SDRAM Width *");
printf("%-3d : %02x %s\n", 14, spd->ecw,
" spd->ecw, * 14 Error Checking SDRAM width *");
printf("%-3d : %02x %s\n", 15, spd->min_delay,
" spd->min_delay, * 15 Back to Back Random Access *");
printf("%-3d : %02x %s\n", 16, spd->burstl,
" spd->burstl, * 16 Burst Lengths Supported *");
printf("%-3d : %02x %s\n", 17, spd->nbanks,
" spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
printf("%-3d : %02x %s\n", 18, spd->cas_lat,
" spd->cas_lat, * 18 CAS# Latencies Supported *");
printf("%-3d : %02x %s\n", 19, spd->cs_lat,
" spd->cs_lat, * 19 Chip Select Latency *");
printf("%-3d : %02x %s\n", 20, spd->write_lat,
" spd->write_lat, * 20 Write Latency/Recovery *");
printf("%-3d : %02x %s\n", 21, spd->mod_attr,
" spd->mod_attr, * 21 SDRAM Module Attributes *");
printf("%-3d : %02x %s\n", 22, spd->dev_attr,
" spd->dev_attr, * 22 SDRAM Device Attributes *");
printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
" spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
printf("%-3d : %02x %s\n", 24, spd->clk_access2,
" spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
" spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
printf("%-3d : %02x %s\n", 26, spd->clk_access3,
" spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
printf("%-3d : %02x %s\n", 27, spd->trp,
" spd->trp, * 27 Min Row Precharge Time (tRP)*");
printf("%-3d : %02x %s\n", 28, spd->trrd,
" spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
printf("%-3d : %02x %s\n", 29, spd->trcd,
" spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
printf("%-3d : %02x %s\n", 30, spd->tras,
" spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
printf("%-3d : %02x %s\n", 31, spd->bank_dens,
" spd->bank_dens, * 31 Density of each bank on module *");
printf("%-3d : %02x %s\n", 32, spd->ca_setup,
" spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
printf("%-3d : %02x %s\n", 33, spd->ca_hold,
" spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
printf("%-3d : %02x %s\n", 34, spd->data_setup,
" spd->data_setup, * 34 Data signal input setup time *");
printf("%-3d : %02x %s\n", 35, spd->data_hold,
" spd->data_hold, * 35 Data signal input hold time *");
printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
" spd->res_36_40[0], * 36 Reserved / tWR *");
printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
" spd->res_36_40[1], * 37 Reserved / tWTR *");
printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
" spd->res_36_40[2], * 38 Reserved / tRTP *");
printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
" spd->res_36_40[3], * 39 Reserved / mem_probe *");
printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
" spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
printf("%-3d : %02x %s\n", 41, spd->trc,
" spd->trc, * 41 Min Active to Auto refresh time tRC *");
printf("%-3d : %02x %s\n", 42, spd->trfc,
" spd->trfc, * 42 Min Auto to Active period tRFC *");
printf("%-3d : %02x %s\n", 43, spd->tckmax,
" spd->tckmax, * 43 Max device cycle time tCKmax *");
printf("%-3d : %02x %s\n", 44, spd->tdqsq,
" spd->tdqsq, * 44 Max DQS to DQ skew *");
printf("%-3d : %02x %s\n", 45, spd->tqhs,
" spd->tqhs, * 45 Max Read DataHold skew tQHS *");
printf("%-3d : %02x %s\n", 46, spd->res_46,
" spd->res_46, * 46 Reserved/ PLL Relock time *");
printf("%-3d : %02x %s\n", 47, spd->dimm_height,
" spd->dimm_height * 47 SDRAM DIMM Height *");
printf("%-3d-%3d: ", 48, 61);
for (i = 0; i < 14; i++)
printf("%02x", spd->res_48_61[i]);
printf(" * 48-61 IDD in SPD and Reserved space *\n");
printf("%-3d : %02x %s\n", 62, spd->spd_rev,
" spd->spd_rev, * 62 SPD Data Revision Code *");
printf("%-3d : %02x %s\n", 63, spd->cksum,
" spd->cksum, * 63 Checksum for bytes 0-62 *");
printf("%-3d-%3d: ", 64, 71);
for (i = 0; i < 8; i++)
printf("%02x", spd->mid[i]);
printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
printf("%-3d : %02x %s\n", 72, spd->mloc,
" spd->mloc, * 72 Manufacturing Location *");
printf("%-3d-%3d: >>", 73, 90);
for (i = 0; i < 18; i++)
printf("%c", spd->mpart[i]);
printf("<<* 73 Manufacturer's Part Number *\n");