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ddr

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  • Forked from Reform / reform-boundary-uboot
    26742 commits behind the upstream repository.
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    York Sun authored
    JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
    is not an issue unless some DQ pins are not connected. If a platform uses
    regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
    those floating pins for the second rank. The workaround is to use a known
    good chip select for this purpose.
    
    Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
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