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nand_spl

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  • Forked from Reform / reform-boundary-uboot
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    Dave Liu authored
    We load the secondary stage u-boot image from NAND to
    system memory by nand_load, but we did not flush d-cache
    to memory, nor invalidate i-cache before we jump to RAM.
    When the system has cache enabled and the TLB/page attribute
    of system memory is cacheable, it will cause issues.
    
    - 83xx family is using the d-cache lock, so all of d-cache
      access is cache-inhibited. so you can't see the issue.
    - 85xx family is using d-cache, i-cache enable, partial
      cache lock. you will see the issue.
    
    This patch fixes the cache issue.
    
    Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
    Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
    c70564e6
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