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examples

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  • Forked from Reform / reform-boundary-uboot
    12851 commits behind the upstream repository.
    user avatar
    Chris Zankel authored
    The Xtensa processor architecture is a configurable, extensible,
    and synthesizable 32-bit RISC processor core provided by Cadence.
    
    This is the first part of the basic architecture port with changes to
    common files. The 'arch/xtensa' directory, and boards and additional
    drivers will be in separate commits.
    
    Signed-off-by: default avatarChris Zankel <chris@zankel.net>
    Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
    Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
    Reviewed-by: default avatarTom Rini <trini@konsulko.com>
    de5e5cea
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    api
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