An error occurred while fetching folder content.
Forked from
Reform / reform-boundary-uboot
Source project has a limited visibility.
York Sun
authored
Some DDR registers' fields have expanded to accommodate larger values. These changes are backward compatible. Some fields are removed for newer DDR controllers. Writing to those fields are safely ignored. TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE automatically. It was a misunderstanding in commit c360ceac. Signed-off-by:York Sun <yorksun@freescale.com>
| Name | Last commit | Last update |
|---|---|---|
| .. | ||