- Sep 30, 2017
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Kever Yang authored
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by:
Kever Yang <kever.yang@rock-chips.com> Acked-by:
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by:
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Kever Yang authored
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by:
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Kever Yang authored
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by:
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Kever Yang authored
Since we have CONFIG_RAM framwork and its driver folder, move the driver into it. Signed-off-by:
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Philipp Tomsich authored
Enable the Rockchip SARADC driver for all Rockchip SoCs. Note that the SARADC peripheral is available on all SoCs except the RK3036 and RK3228. However, as this is a DM-driver, enabling by default will not cause any function problems (and can always be changed from defconfig, if size is a concern). Signed-off-by:
David Wu <david.wu@rock-chips.com>
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David Wu authored
Enable the SARADC for download key pressed detect. Signed-off-by:
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David Wu authored
Enable the SARADC for download key pressed detect. Signed-off-by:
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David Wu authored
Enable the SARADC for download key pressed detect. Signed-off-by:
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David Wu authored
Enable the SARADC for download key pressed detect. Signed-off-by:
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David Wu authored
Enable the SARADC for download key pressed detect. Signed-off-by:
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David Wu authored
Enable the SARADC for download key pressed detect. Signed-off-by:
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David Wu authored
Signed-off-by:
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David Wu authored
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by:
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David Wu authored
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by:
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- Sep 29, 2017
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Karthik Tummala authored
This re-syncs omap3 DTS file with current file from Linux v4.14-rc1 to ensure a consistent configuration. Upstream Linux removed the redundant Interrupt-parent property from usbhsohci, usbhsehci, ssi_port1 and ssi_port2 sub nodes. Signed-off-by:Karthik Tummala <karthik@techveda.org>
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Lokesh Vutla authored
With DM enabled, gpio numbering is assigned based on the probed order of gpios, irrespective of the gpio base. So enable all necessary gpios in SPL. Fixes: edf25d94d55c (“ARM: dts: OMAP5+: Enable gpio in SPL”) Reported-by:
Gou, Hongmei <h-gou@ti.com> Tested-by:
Aparna Balasubramanian <aparnab@ti.com> Signed-off-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
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Madan Srinivas authored
This patch adds support for authentication of both plain text and encrypted binaries. A new SECDEV package is needed to enable encryption of binaries by default for AM3x. The ROM authentication API detects encrypted images at runtime and automatically decrypts the image if the signature verification passes. Addition of encryption on AM3x results in a change in the image format. On AM4x, AM5x and, on AM3x devices signing clear test images, the signature is appended to the end of the binary. On AM3x, when the SECDEV package is used to create signed and encrypted images, the signature is added as a header to the start of the binary. So the binary size calculation has been updated to reflect this change. The signing tools and encrypted image format for AM3x cannot be changed to behave like AM4x and AM5x to maintain backward compatibility with older Sitara M-Shield releases. Signed-off-by:
Madan Srinivas <madans@ti.com> Signed-off-by:
Andrew F. Davis <afd@ti.com>
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Adam Ford authored
With the device tree ported from Linux 4.13, this enables Driver Model and Device Tree support for the am3517-evm Signed-off-by:
Adam Ford <aford173@gmail.com> Tested-by:
Derald D. Woods <woods.technical@gmail.com>
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Adam Ford authored
To keep the DTS and DTSI files clean and in sync with Linux, new u-boot.dtsi files are added. There are some spacing issues in the patch, but they appear to be present in the Linux source files. I'll try to get to fixing them there, and do a future re-sync at a later date. Signed-off-by:
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Tom Rini authored
On ARCH_OMAP2PLUS platforms we know what the DDR layout is going to be, and that it is safe to use SPL_STACK_R and provide a default value for it. select this and re-sync the defconfigs. Signed-off-by:Tom Rini <trini@konsulko.com>
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Adam Ford authored
With DM now enabled with the device tree pulled from Linux, we can enable DM_I2C in U-Boot. Reviewed-by:
Jagan Teki <jagan@openedev.com> Signed-off-by:
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Adam Ford authored
A few small additional items are needed to support DM_SPI and DM_SERIAL, so those were added to da850-evm-u-boot.dtsi Signed-off-by:
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- Sep 28, 2017
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rick authored
It is caused from asm/io.h declare different input type. Signed-off-by:rick <rick@andestech.com>
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- Sep 26, 2017
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Baruch Siach authored
The ClearFog Base boot from UART when setting the DIP switches to 01001. Unfortunately, the SPL code sometimes fails to detect the UART boot method at run-time. Add an alternative SAR UART boot value to fix this. Note that this alternative value is not documented (Armada 38x Hardware Specifications, Table 48). But experimentations showed it on the ClearFog Base. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
Stefan Roese <sr@denx.de>
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Chris Packham authored
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not work because mvebu_sdram_bs() returns 0 and the code was subtracting 1 before checking the size. Remove the -1 from the bank size and the +1 from the total which will skip unused banks and still calculate the correct size. Put the -1 where it is needed for scrubbing via the xor engine. Reported-by:
Joshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by:
Chris Packham <judge.packham@gmail.com> Signed-off-by:
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Chris Packham authored
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these variants to the sar_freq_tab. Signed-off-by:
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Joshua Scott authored
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled) Signed-off-by:
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Chris Packham authored
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs. Signed-off-by:
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Chris Packham authored
This converts the following to Kconfig: CONFIG_MVNETA Signed-off-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
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- Sep 23, 2017
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Masahiro Yamada authored
GCC 7.1 warns: duplicate ‘const’ declaration specifier [-Wduplicate-decl-specifier] Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com>
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- Sep 22, 2017
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Sriram Dash authored
I2C code is put under CONFIG_SYS_I2C. Signed-off-by:
Sriram Dash <sriram.dash@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Sriram Dash authored
IFC code is put under CONFIG_FSL_IFC Signed-off-by:
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Santan Kumar authored
As per updated board design, different QSPI flash is connected on boards, hence change QSPI flash type from Micron n25q512a device to spansion s25fs512s device in dts and config. Signed-off-by:
Santan Kumar <santan.kumar@nxp.com> Signed-off-by:
Yogesh Gaur <yogeshnarayan.gaur@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by:
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Ashish Kumar authored
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by:
Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by:
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Felix Brack authored
This patch provides default implementations of the two functions set_uart_mux_conf and set_mux_conf_regs. Hence boards not using them do not need to provide their distinct empty definitions. Signed-off-by:
Felix Brack <fb@ltec.ch> Reviewed-by:
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Patrice Chotard authored
This patch adds support for stm32h7 soc family, stm32h743 discovery and evaluation boards. For more information about STM32H7 series, please visit: http://www.st.com/en/microcontrollers/stm32h7-series.html Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Reviewed-by:
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Patrice Chotard authored
This patch adapts stm32h743 disco and eval dts files to match with U-boot requirements or add features wich are not yet upstreamed on kernel side : _ Add RCC clock driver node and update all clocks phandle accordingly. By default, on kernel side, all clocks was temporarly configured as a phandle to timer_clk waiting for a RCC clock driver to be available. On U-boot side, we now have a dedicated RCC clock driver, we can configured all clocks as phandle to this driver. All this binding update will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html _ Align STM32H7 serial compatible string with the one which will be available in next kernel tag. The bindings has been acked by Rob Herring [2]. This compatible string will be usefull to add stm32h7 specific feature for this serial driver. [2] https://lkml.org/lkml/2017/7/17/739 _ Add gpio compatible and aliases for stm32h743 _ Add FMC sdram node with associated new bindings value to manage second bank (ie bank 1). _ Add missing HSI and CSI oscillators nodes needed by STM32H7 RCC clock driver. Clock sources could be: _ HSE (High Speed External) _ HSI (High Speed Internal) _ CSI (Low Power Internal) These clocks can be used as clocksource in some configuration. By default, HSE is selected as clock source. _ Set HSE to 25Mhz for stm32h743i-disco and eval board By default, the external oscillator frequency is defined at 25 Mhz in SoC stm32h743.dtsi file. It has been set at 125 Mhz in kernel DT temporarly waiting for RCC clock driver becomes available. As in U-boot we got a RCC clock driver, the real value of HSE clock can be used. _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes. Signed-off-by:
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Patrice Chotard authored
This file is imported from linux kernel v4.13 Add device tree support for STM32H743 evaluation board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS and FS _ I2 C compatible serial interface _ RTC with rechargeable backup battery _ SAI Audio DAC _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash _ 1-Gbit Twin Quad-SPI NOR Flash _ Potentiometer _ 4 colored user LEDs _ Reset, wakeup, tamper or key buttons _ Joystick with 4-direction control and selector _ Board connectors : Power jack 3 USB with Micro-AB RS-232 communications Ethernet RJ45 FD-CAN compliant connection Stereo headset jack including analog microphone input 2 audio jacks for external speakers microSD™ card JTAG/SWD and ETM trace _ Expansion connectors: Extension connectors and memory connectors for daughterboard or wire-wrap board _ Flexible power-supply options: ST-LINK USB VBUS or external sources _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by: -
Patrice Chotard authored
All these files are imported from linux kernel v4.13 Add device tree support for STM32H743 SoC and discovery board. This board offers : _ STM32H743XIH6 microcontroller with 2 Mbytes of Flash memory and 1 Mbyte of RAM in TFBGA240+25 package _ 5.7” 640x480 TFT color LCD with touch screen _ Ethernet compliant with IEEE-802.3-2002 _ USB OTG HS _ I2 C compatible serial interface _ ST-MEMS digital microphones _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card _ 8Mx32bit SDRAM _ 1-Gbit Twin Quad-SPI NOR Flash _ Reset, wakeup, or key buttons _ Joystick with 4-direction control and selector _ Board connectors : 1 USB with Micro-AB Ethernet RJ45 Stereo headset jack including analog microphone input microSD™ card RCA connector JTAG/SWD and ETM trace _ Expansion connectors: Arduino Uno compatible Connectors 2 x PIO connectors (PMOD and PMOD+) _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port Signed-off-by:Vikas Manocha <vikas.manocha@st.com> Reviewed-by:
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Patrice Chotard authored
Update ehci and ohci node's compatible string in order to use ehci-generic and ohci-generic drivers. Signed-off-by:
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