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  1. Sep 10, 2012
  3. Sep 06, 2012
    • Benoît Thébaudeau's avatar
      mx31: Define default SoC input clock frequencies · 0dc7b82e
      Benoît Thébaudeau authored 
      
Define default SoC input clock frequencies for i.MX31 in order to get rid of
duplicated definitions.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Helmut Raiger <helmut.raiger@hale.at>
      0dc7b82e
    • Marek Vasut's avatar
      MX28: MMC: Avoid DMA DCache race condition · 97ed12ce
      Marek Vasut authored 
      
This patch prevents dcache-related problem. The problem manifested
itself on the SPI driver, this is just a port to the MMC driver.

The scenario is the same. In case an "mmc read" is issued to a
buffer which was written right before it and data cache is enabled,
the cache eviction might happen during the DMA transfer into the
buffer, therefore corrupting the buffer. Clear any cache lines that
might contain the buffer to prevent such issue.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
      97ed12ce
    • Marek Vasut's avatar
      MX28: SPI: Fix the DMA chaining · e9f7eafd
      Marek Vasut authored 
      
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.

Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.

Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.

Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
      e9f7eafd
    • Marek Vasut's avatar
      MX28: SPI: Fix the DMA DCache race condition · 88d15559
      Marek Vasut authored 
      
This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:

mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000

The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.

It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.

On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
      88d15559
    • Benoît Thébaudeau's avatar
      Fix mx31_decode_pll · 697191d5
      Benoît Thébaudeau authored 
      
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
      697191d5
    • Benoît Thébaudeau's avatar
      mx35 timer: Switch to 32-kHz source · 543d2479
      Benoît Thébaudeau authored 
      
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: default avatarStefano Babic <sbabic@denx.de>
      543d2479
    • Benoît Thébaudeau's avatar
      mx35: Define default SoC input clock frequencies · 9c6c5c06
      Benoît Thébaudeau authored 
      
Define default SoC input clock frequencies for i.MX35 in order to get rid of
duplicated definitions.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: default avatarStefano Babic <sbabic@denx.de>
      9c6c5c06
    • Benoît Thébaudeau's avatar
      mx25: Define default SoC input clock frequencies · 1b2080f3
      Benoît Thébaudeau authored 
      
Define default SoC input clock frequencies for i.MX25 in order to get rid of
duplicated definitions.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Matthias Weisser <weisserm@arcor.de>
      1b2080f3
    • Benoît Thébaudeau's avatar
      mx35: Fix clock dividers · 82e1b543
      Benoît Thébaudeau authored 
      
The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
      82e1b543
    • Benoît Thébaudeau's avatar
      mx35: Add definitions for clock gate values · 9ba81baa
      Benoît Thébaudeau authored 
      
Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
      9ba81baa
    • Benoît Thébaudeau's avatar
      mx35: Fix decode_pll · e7619554
      Benoît Thébaudeau authored 
      
The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.

Signed-off-by: default avatarBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
      e7619554
  5. Sep 04, 2012
  7. Sep 03, 2012
  9. Sep 01, 2012