Add a new command 'wol': Wait for an incoming Wake-on-LAN packet or
time out if no WoL packed is received.
If the WoL packet contains a password, it is saved in the environment
variable 'wolpassword' using the etherwake format (dot or colon
separated decimals).

Intended use case: a networked device should boot an alternate image.
It's attached to a network on a client site, modifying the DHCP server
configuration or setup of a tftp server is not allowed.
After power on the device waits a few seconds for a WoL packet. If a
packet is received, the device boots the alternate image. Otherwise
it boots the default image.

This method is a simple way to interact with a system via network even
if only the MAC address is known. Tools to send WoL packets are
available on all common platforms.

Some Ethernet drivers seem to pad the incoming packet. The additional
padding bytes might be recognized as Wake-on-LAN password bytes.

By default enabled in pengwyn_defconfig.

Signed-off-by: Lothar Felten <lothar.felten@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Make the initialization sequence consistent with the Linux kernel
driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>

This fixes sporadic timeout on initial packet Tx (usually ARP), with an
error message like:

  timeout: packet not sent

Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>

When building without FASTBOOT_FLASH we don't include the intermediate
update callback to keep the client alive, so ensure we don't try setting
it here.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

As pointed out by Wolfgang Denk, the problem with this fix is that while
interactive users will see that we have found one part of the
environment failed and are using the other, progmatic use will not see
this and can lead to problems.

Signed-off-by: Tom Rini <trini@konsulko.com>

This updates the doc to mention chain-loading an x86 kernel via
'bootefi' command, along with several typos fix.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexander Graf <agraf@suse.de>

CONFIG_EFI_LOADER is fully supported on x86 now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexander Graf <agraf@suse.de>

Output ACPI configuration table if it exists.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

ACPI tables can be passed via EFI configuration table to an EFI
application. This is only supported on x86 so far.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

At present the number of configuration tables is set to 2. By
looking at which tables the Linux EFI stub or iPXE can process,
it looks 16 is a reasonable number.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

On x86 traditional E820 table is used to pass the memory information
to kernel. With EFI loader we can build the EFI memory map from it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.

If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

This adds the scsi command to coreboot and qemu, to be in consistent
with other x86 targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.

This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

On a 4.18-rc1 kernel the following warning is seen on i.MX51 and
i.MX53:

CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53
to fix the problem.

With this patch applied the kernel reports:

CPU0: Spectre v2: using BPIALL workaround

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

%s/reminder/remainder/

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>

Enable CVE-2017-5715 option to set the IBE bit. This enables kernel
workarounds necessary for the said CVE.

With this enabled, Linux reports:
CPU0: Spectre v2: using BPIALL workaround

This workaround may need to be re-applied in OS environment around low
power transition resume states where context of ACR would be lost (off-mode
etc).

Signed-off-by: Nishanth Menon <nm@ti.com>

ARM: mach-omap2: omap5/dra7: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS

Enable CVE_2017_5715 and since we have our own v7_arch_cp15_set_acr
function to setup the bits, we are able to override the settings.

Without this enabled, Linux kernel reports:
CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable

With this enabled, Linux kernel reports:
CPU0: Spectre v2: using ICIALLU workaround

NOTE: This by itself does not enable the workaround for CPU1 (on
OMAP5 and DRA72/AM572 SoCs) and may require additional kernel patches.

Signed-off-by: Nishanth Menon <nm@ti.com>

As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB)
needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to
be done unconditionally for Cortex-A15 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.

NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
   provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the
   right locations.
c) This workaround applies to only the boot processor. It is important
   to apply workaround as necessary (context-save-restore) around low
   power context loss OR additional processors as necessary in either
   firmware support OR elsewhere in OS.

[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html



Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andre Przywara <Andre.Przywara@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

As recommended by Arm in [1], IBE[2] has to be enabled unconditionally
for BPIALL to be functional on Cortex-A8 processors. Provide a config
option for platforms to enable this option based on impact analysis
for products.

NOTE: This patch in itself is NOT the final solution, this requires:
a) Implementation of v7_arch_cp15_set_acr on SoCs which may not
   provide direct access to ACR register.
b) Operating Systems such as Linux to provide adequate workaround in the right
   locations.
c) This workaround applies to only the boot processor. It is important
   to apply workaround as necessary (context-save-restore) around low
   power context loss OR additional processors as necessary in either
   firmware support OR elsewhere in OS.

[1] https://developer.arm.com/support/security-update
[2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html



Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Andre Przywara <Andre.Przywara@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com>

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

This patch update the USB PHY index for Allwinner H3.

Same change[1] initially sent, by 'Chen-Yu Tai' but missed
to apply due to recursive version changes on the same series.

[1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.html



Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>

ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.

Fixes 831cc98b ("usb: sunxi: Simplify ccm reg base code")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>

This bug is the combination of dwc2 USB controller and lan78xx
USB ethernet controller, which is the combination in use on
the Raspberry Pi Model 3 B+.

When the host attempts to receive a packet, but a packet has not
arrived, the lan78xx controller responds by setting BIR
(Bulk-In Empty Response) to NAK. Unfortunately, this hangs
the USB controller and requires the USB controller to
be reset.

The fix proposed is to have the lan78xx controller respond
by setting BIR to ZLP.

Signed-off-by: Andrew Thomas <andrew.thomas@oracle.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>

When using a redundant environment a read error should simply mean to
not use that copy instead of giving up completely. The other copy may
be just fine.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Ioan-Adrian Ratiu <adrian.ratiu@ni.com>

This fixes the warnings:

WARNING: no status info for 'ge_bx50v3'
WARNING: no maintainers for 'ge_bx50v3

Signed-off-by: Stefano Babic <sbabic@denx.de>

For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.

For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.

The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>

The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.

A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>

Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list
to identify the NAND flash in SPL.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>

`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>

Since commit 1da1938d ("spl: Add default values for ARCH_MX7")
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is selected by default on
i.MX7 platforms, so remove it from the board defconfig.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

fdt_file is looking for imx6ul-geam-kit.dtb but Linux
has imx6ul-geam.dtb, since Linux skipped -kit on file name
by below commit.
"ARM: dts: imx6ul-geam: Skip suffix -kit from dts name"
(sha1: 182de5ebce71e469cfa686fcdf08c9cbe11ece97)

So, due to this mismatch U-Boot failed to pick the
proper dtb which eventually break the Linux boot.

This patch fixed this mismatch by
- renaming dts files
- update config option to use new dtb file
- update fdt_file to new dtb file name

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

The PFUZE3000 uses registers addresses up to 0xff.

The DM pfuze100 driver supports both pfuze100 and pfuze3000.  Allow it
to use the device type to return the correct number of registers.

Also rename the too generic PMIC_NUM_OF_REGS enumeration value for
pfuze3000 to match the other "PFUZE3000_" prefixed enumerations and the
pfuze100 enumeration value PFUZE100_NUM_OF_REGS.

Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>