Fix the problem that cannot access actual data when CPU data cache enabled.

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Tested-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>

For a long time, the print_cpuinfo() declaration in lib_arm/board.c
had been marked as "test-only", which is plain wrong considering
current usage.  Delete this misleading comment.

Signed-off-by: Wolfgang Denk <wd@denx.de>

if using CONFIG_BOOTCOUNT_LIMIT feature on a MPC8360 CPU
in the muram-data node, the reg entry needs to be updated.
This is done in fdt_fixup_muram(), but we should use
the compatible "fsl,qe-muram-data" for searching the
node instead of searching the muram-data node with
an absolute path.

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

The size of U-Boot binary for MPC8360ERDK increased
(> 2 flash sectors now), so 'saveenv' will partially
overwrite U-Boot in flash and will brick the board.
This patch moves environment offset to fourth flash
sector and also fixes CONFIG_SYS_MONITOR_LEN.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

The patch fixes the bug of partial initialization of global network
parameters.

Upon u-boot's start up the first ping command causes a failure of the
consequent TFTP command. It happens in the recently added mechanism of
the NetLoop initialization where initialization of global network
parameters is separated in the NetInitLoop routine which is called per
env_id change. Thus, ping request will initialize the network parameters
necessary for ping operation only, afterwards the env_changed_id will be
set to the env_id that will prevent all following initialization requests
from other protocols.
The problem is that the initialized by ping subset of network parameters
is not sufficient for other protocols and particularly for TFTP which
requires the NetServerIp also.

Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Change netdev.h to use CONFIG_ULI526X instead of CONFIG_ULI526.  CONFIG_ULI526X
is used everywhere else, so that's the correct macro name.  Without this fix,
Ethernet will not work on the Freescale MPC8610 HPCD.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

Update the DaVinci DM6446 boards to use the new convention
for CONFIG_SYS_NS16550_REG_SIZE ... the size hasn't changed
from the original 4 bytes, but these chips are little-endian.

(Resolves a regression added recently by the include/ns16550.h
patch to "Unify structure declaration for registers".  The code
previously worked just fine because the registers were accessed
as host-endian words, not as bytes.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

The first if statement checks for NULL ptrs, so there is no need to check
it again in later else cases (such as .oob).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Scott Wood <scottwood@freescale.com>

Fix dependency goofage:  it should certainly be possible to have the
partition support without bringing in UBI commands.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Acked-by: Stefan Roese <sr@denx.de>

The timer has been rewrote with a precision at ~0,18%

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Tested-by: Sergey Lapin <slapin@ossfans.org>
Tested-by: Eric BENARD <ebenard@free.fr>

The PM9263 board is based on the AT91SAM9263-EK board.

Here is the page on Ronetix website:
http://www.ronetix.at/starter_kit_9263.html



Signed-off-by: Ilko Iliev <iliev@ronetix.at>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

calculate dynamically the clock rate and pllb setting for usb

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Don't run the memory POST on the NAND-booting version. It will
overwrite part of the U-Boot image which is already loaded from NAND
to SDRAM. We were just lucky that it booted at all with this SDRAM
test enabled.

Signed-off-by: Stefan Roese <sr@denx.de>

Don't run the memory POST on the NAND-booting version. It will
overwrite part of the U-Boot image which is already loaded from NAND
to SDRAM. We were just lucky that it booted at all with this SDRAM
test enabled.

Signed-off-by: Stefan Roese <sr@denx.de>

The current define of get_bus_freq() in the CONFIG_NAND_SPL #ifdef is not
used at all. This patch changes it's define to the currently used value of
133333333 and removes the unnecessary code.

Signed-off-by: Stefan Roese <sr@denx.de>

This additional text in the bootup log helps to see if the board is
configured for NAND-booting. Especially helpful for boards that can
boot from NOR and NAND (e.g. most of the AMCC eval boards).

Signed-off-by: Stefan Roese <sr@denx.de>

Currently the NOR & NAND support in Linux only works for the "standard"
Sequoia, the version booting for NOR flash. The NAND-booting version
has the chip-selects swapped. Here the chip-select mappings:

"Standard" NOR-booting version:
CS0	NOR
CS3	NAND

NAND-booting version:
CS0	NAND
CS3	NOR

With this path the dtb gets fixed-up, so that the correct chip-select
numbers are patched in the dtb enabling correct NOR & NAND support
in Linux on the NAND-booting Sequoia version.

Signed-off-by: Stefan Roese <sr@denx.de>

There is no code change here, just new comments, but this keeps me from
having to do another audit from scratch in the future.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

DESCRIPTION:
The column address width settings for banks 2 and 3 are misconnected in
the SDRAM controller.  Accesses to bank 2 will result in an error if the
Column Address Width for bank 3 (EB3CAW ) is not set to be the same as
that of bank 2.

WORKAROUND:
If using bank 2, make sure that banks 2 and 3 have the same column address
width settings in the EBIU_SDBCTL register.  This must be the case
regardless of whether or not bank 3 is enabled.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

DESCRIPTION:
If the DF bit is set prior to a hardware reset, the PLL will continue to
divide CLKIN by 2 after the hardware reset, but the DF bit itself will be
cleared in the PLL_CTL register.

WORKAROUND:
Reprogram the PLL with DF cleared if the desire is to not divide CLKIN by
2 after reset.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

DESCRIPTION:
The Boot ROM is executed at power up/reset and changes the value of the
SICA_IWR registers from their default reset value of 0xFFFF, but does not
restore them.

WORKAROUND:
User code should not rely on the default value of these registers.  Set
the desired values explicitly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

We need to make sure the data written to the nand flash controller makes
it there before we start polling its status register.  Otherwise, we may
get stale data and return before the controller is actually ready.

Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Scott Wood <scottwood@freescale.com>

	This Patch adds Support for PXA27X UDC.
	(Rebased to drivers/usb reorganisation)

Signed-off-by: Vivek Kutal <vivek.kutal@azingo.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>

move to linux usb driver organisation

as following

drivers/usb/gadget
drivers/usb/host
drivers/usb/musb

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>

Blackfin SPI driver was not driving the SPI chip-select high before
putting the chip-select signals into tri-state mode.  This is probably
something that slipped by unnoticed in most designs.  If the signals are
put directly into a tri-state mode, then the board is relying on the
pull-up resistors to pull up the chip-select before the next transaction.
Most of the time this is fine, except when you have two transactions that
follow each other very closely, such as the flash erase and read status
register commands.  In this case I was seeing a 500ns separation between
the transactions.  In my setup, with a 10kOhm pull-up, it would meet
timing spec about half the time and resulted in intermittent errors.  (A
stronger pull up would fix this, but our design is targeted for low power
consumption and a 3.3kOhm @ 3.3v is 3.3mW of needless power consumption.)
I modified the spi_cs_deactivate() function in bfin_spi.c to drive the
chip-selects high before putting them into tri-state.  For me, this
resulted in a rise time of 5ns instead of the previous rise time of about
1us, and fully satisfied the timing spec of the chip.

Signed-off-by: Todor I Mollov <tmollov@ucsd.edu>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

A new Overo expansion board uses GPIO 14, 21, 22 and 23 for LED's and
switches. This patch changes the pinmux configuration for those pins.
They were previously set up for unused MMC3_DAT4-7.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

unify arm cache management except for non standard cache as ARM7TDMI

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

import system.h from linux

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

imx31_phycore_eet is a variant of the imx31_phycore board with a few
extensions, which justifies a separate entry in the MAINTAINERS list,
whereas normally all entries sharing a single configuration file and a
board/ directory have only one entry in MAINTAINERS.

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

Fix out-of-tree build of the imx31_phycore_eet target.

Reported-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Guennadi Liakhovetski <lg@denx.de>

The previous code waited 1000us before checking i2c
status. Measurement shows i2c is usually ready in
under 50us. Change the polling interval to 15us,
loop 6,667 times to keep the polling timeout constant
at 100ms.