Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP4 board select menu to omap4/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap4").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the OMAP3 board select menu to omap3/Kconfig.

Move also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="omap3

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the Davinci board select menu to davinci/Kconfig.

Move also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="davinci").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the Exynos board select menu to exynos/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="exynos").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the KirkWood board select menu to kirkwood/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and
CONFIG_SYS_SOC="kirkwood").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Prafulla Wadasdkar <prafulla@marvell.com>
Cc: Luka Perkov <luka@openwrt.org>

Move Versatile-specific settings to versatile/Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the Rmobile board select menu to rmobile/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="rmobile").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the Tegra board select menu to tegra/Kconfig.

Insert the Tegra SoC select menu between the arch select and the
board select.

 Architecture select
 |-- Tegra Platform (Tegra)
     |- Tegra SoC select (Tegra20 / 30 / 114 / 124)
        |- Board select

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows:

  config TEGRA
          bool
          select SPL

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>

Becuase the board select menu in arch/arm/Kconfig is too big,
move the Zynq board select menu to zynq/Kconfig.

Consolidate also common settings (CONFIG_SYS_CPU="armv7" and
CONFIG_SYS_SOC="zynq").

Refactor board/xilinx/zynq/MAINTAINERS too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>

Commit 41623c91 'arm: move exception handling out of start.S files' missed some
linker scripts. Hence, some boards no longer had exception handling linked since
this commit. Restore the original behavior by adding the .vectors section to
these linker scripts.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

The Documentation/arm64/booting.txt document says that pass in x1/x2/x3
as 0 as they are reserved for future use.

Signed-off-by: Tom Rini <trini@ti.com>

Convert the bcm958300k and the bcm958622hr boards from "boards.cfg" to Kconfig.

Signed-off-by: Steve Rae <srae@broadcom.com>

The bcm_ep board configuration is used by a number of boards
including Cygnus and NSP.
Add builds for the bcm958300k and the bcm958622hr boards.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

Base support for the Broadcom NSP SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

Base support for the Broadcom Cygnus SoC.
Based on iproc-common and the SoC specific reset function.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

The iproc architecture code is present in several Broadcom
chip architectures, including Cygnus and NSP.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

Add NFC (NAND Flash Controller) clock support and enable them
at board initialization time.

Signed-off-by: Stefan Agner <stefan@agner.ch>

Add pin mux for NAND Flash Controller (NFC). NAND can be connected
using 8 or 16 data lines, this patch adds pin mux entries for all
16 data lines.

Signed-off-by: Stefan Agner <stefan@agner.ch>

The patch fixes a corner case where adding size to DRAM start resulted
in a value (1 << 32), which in turn overflew the u32 computation, which
resulted in 0 and it therefore prevented correct setup of the MMU tables.

The addition of DRAM bank start and it's size can end up right at the end
of the address space in the special case of a machine with enough memory.
To prevent this overflow, shift the start and size separately and add them
only after they were shifted.

Hopefully, we only have systems in tree which have DRAM size aligned to
1MiB boundary. If not, this patch would break such systems. On the other
hand, such system would be broken by design anyway.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>

Enable Ethernet clock when Broadcom StarFighter2 Ethernet block
(CONFIG_BCM_SF2_ETH) is enabled.

Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>

However ep9315 don't use
interrupt vectors during startup, but _startup symbol is used inside uboot to
calculate actual monitor size.

Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net

Enable initialization fo designware ethernet controller. With this
patch, ethernet works in my configuration, provided I set ethernet
address in the environment.

Signed-off-by: Pavel Machek <pavel@denx.de>

To fix the build error when build for Altera dev kit, not
virtual target. At same time, set the build for Altera dev
kit as default instead virtual target. With that, U-Boot
is booting well and SPL still lack of few drivers.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

Structure defining clock manager hardware was wrong, leading to
wrong registers being accessed and hang in MMC init.

This fixes structure to match hardware.

Signed-off-by: Pavel Machek <pavel@denx.de>

config.h is required for CONFIG_SYS_DV_NOR_BOOT_CFG.

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>

When compiling u-boot with W=1 the extern inline void for
read* is likely causing the most noise. gcc / clang will
warn there is never a actual declaration for these functions.
Instead of declaring these extern make them static inline so
it is actually declared.

cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>

DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination
and this is controlled by gpio7_11. Configuring gpio7_11.
The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards,
and left unused on previous boards, so it is safe enough to enable gpio
on all DRA7 boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

This patch reads EFUSE_BOOTROM register to see the maximum supported
clock for CORE and TETRIS PLLs and configure them accordingly.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM.
The Flash device is connected to GPMC controller on chip-select[0] and accessed
as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and
is CFI compatible.

As multiple devices are share GPMC pins on this board, so following board
settings are required to detect NOR device:
     SW5.1 (NAND_BOOTn) = OFF (logic-1)
     SW5.2 (NOR_BOOTn)  = ON  (logic-0) /* Active-low */
     SW5.3 (eMMC_BOOTn) = OFF (logic-1)
     SW5.4 (QSPI_BOOTn) = OFF (logic-1)

And also set appropriate SYSBOOT configurations:
     SW3.1 (SYSBOOT[ 8])= ON  (logic-1) /* selects SYS_CLK1 speed */
     SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */
     SW3.3 (SYSBOOT[10])= ON  (logic-1) /* wait-pin monitoring = enabled */
     SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */
     SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */
     SW3.6 (SYSBOOT[13])= ON  (logic-1) /* device bus-width: 1(x16) */
     SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */
     SW3.8 (SYSBOOT[15])= ON  (logic-1) /* reserved */

Also, following changes are required to enable NOR Flash support in
dra7xx_evm board profile:

Emails to the board maintainer
"Rishi Bhattacharya <rishi@ti.com>"
have been bouncing.

Tom suggested to remove this board.

Remove also omap1510_udc.c because this is the last board
to enable it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Suggested-by: Tom Rini <trini@ti.com>

mx6sxsabresd board has 2 FEC ports, each one connected to a AR8031.

Add support for one FEC port initially.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Configure and enable the ethernet clock for mx6solox.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

mx6sxsabresd was not in the master branch when the conversion to the new Kconfig
style happened, so convert it now so that it can build again.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

The COL field value cannot be easily calculated from the desired
column number. Instead, there are special cases for that, see the
datasheet, MMDCx_MDCTL field description, field COL . Cater for
those special cases.

Signed-off-by: Marek Vasut <marex@denx.de>

The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but
only 3840 MiB of that can be really used. In case the controller is
configured to operate a 4GiB module, the imx_ddr_size() function will
correctly compute that there is 4GiB of DRAM in the system. Firstly,
the return value is 32-bit, so the function will effectively return
zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB
of all that. Thus, clamp the returned size to 3840MiB in such case.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>

Fix the name of the CCM CHSCCDR register.

Signed-off-by: Marek Vasut <marex@denx.de>

This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Stefano Babic <sbabic@denx.de>

Do not specify own zynq specific SPL macros
because there is no need for that.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Prepare for spl.h removal.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>