- Apr 10, 2011
-
-
Fabian Cenedese authored
Removed clearing of L2 cache as SRAM as it is not necessary without ECC. This also speeds up the booting process. Signed-off-by:
Fabian Cenedese <cenedese@indel.ch> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
-
Priyanka Jain authored
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by:
Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by:
Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by:
Stefano Babic <sbabic@denx.de> Signed-off-by:
-
Shaohui Xie authored
PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by:
Chunhe Lan <b25806@freescale.com> Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Shaohui Xie <b21989@freescale.com> Signed-off-by:
Roy Zang <tie-fei.zang@freescale.com> Signed-off-by:
-
Jiang Yutang authored
Set default configuration to have SDHC controller enabled, AUDIO enabled(codec clock sources is 12MHz) and disable TDM. Signed-off-by:
Jiang Yutang <b14898@freescale.com> Signed-off-by:
-
Jiang Yutang authored
For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by:
-
Jiang Yutang authored
Make the support for ATI graphics cards mutually exclusive with DIU. Signed-off-by:
-
Timur Tabi authored
Remove the SERDES8 erratum work-around code that only applied to P4080 rev1, which is not supported by this version of U-Boot. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
-
Timur Tabi authored
Add documentation for the "serdes" hwconfig option, which is used to specify the status of SerDes banks two and three for the SERDES8 erratum work-around. Signed-off-by:
-
- Apr 09, 2011
-
-
Kumar Gala authored
We don't really ever use Video cards on corenet_ds style boards and its bloating our image which is close the its max size. Drop support and also kill some defines for non-PNP PCI which we never use. Signed-off-by:
-
- Apr 08, 2011
-
-
Matthew McClintock authored
renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more appropriate CONFIG_SYS prefix as well as be consistent with 83xx. Signed-off-by:
Matthew McClintock <msm@freescale.com> cc: Scott Wood <scottwood@freescale.com> Signed-off-by:
-
- Apr 05, 2011
-
-
Zhao Chenhui authored
* Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by:
Zhao Chenhui <b35336@freescale.com> Signed-off-by:
-
Haiying Wang authored
P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
-
Zhao Chenhui authored
Signed-off-by:
Li Yang <leoli@freescale.com> Signed-off-by:
-
git://git.denx.de/u-boot-mpc85xxWolfgang Denk authored
Conflicts: drivers/usb/host/ehci-pci.c Signed-off-by:Wolfgang Denk <wd@denx.de>
-
-
Timur Tabi authored
Clean up the macro defintions used to enable DIU (video) support on the MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS, which is newer. Add software cursor support to all three boards. Also document the CONFIG_FSL_DIU_FB in the README. Signed-off-by:
Anatolij Gustschin <agust@denx.de> Signed-off-by:
-
Jerry Huang authored
We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
-
Mingkai Hu authored
On some boards the environment may not be located at a fixed address in the MMC/SDHC card. This allows those boards to implement their own means to report what address the environment is located at. Signed-off-by:
Andy Fleming <afleming@freescale.com> Signed-off-by:
-
- Apr 04, 2011
-
-
Kumar Gala authored
Signed-off-by: -
Kyle Moffett authored
The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by:
Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by:
York Sun <yorksun@freescale.com> Signed-off-by:
-
Kyle Moffett authored
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies. Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily restructure the computation to use the "do_div()" function to perform 64-bit/32-bit divide operations. On 64-bit this change is basically a no-op, because do_div is implemented as a literal 64-bit divide operation and the instruction scheduling works out almost the same. On 32-bit PowerPC a fully accurate 64/64 divide (__udivdi3 in libgcc) is over 1.1kB of code and thousands of heavily dependent cycles to compute, all of which is linked from libgcc. Another 1.2kB of code comes in for the function __umoddi3. It should be noted that nothing else in U-Boot or the Linux kernel seems to require a full 64-bit divide on my 32-bit PowerPC. Build-and-boot-tested on the HWW-1U-1A board using DDR2 SPD detection. Signed-off-by:
-
Laurentiu TUDOR authored
We utilize the compatible string to find the node to add fsl,liodn property to. However P3041 & P5020 don't have "fsl,p4080-pcie" compatible for their PCIe controllers as they aren't backwards compatible. Allow the macro's to specify the PCIe compatible to use to allow SoC uniqueness. On P3041 & P5020 we utilize "fsl,qoriq-pcie-v2.2" for the PCIe controllers. Signed-off-by:
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> Signed-off-by:
-
Jiang Yutang authored
Signed-off-by:
-
Li Yang authored
Signed-off-by: -
bhaskar upadhaya authored
Fix up the device tree property associated with the IEEE 1588 timer source frequency. Currently we only support the IEEE 1588 timer source being the internal eTSEC system clock (for those SoCs with IEEE 1588 support). The eTSEC clock is ccb_clk/2. Signed-off-by:
Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by:
-
Kumar Gala authored
On the P1023 the Fman freq is equivalent to the system bus freq, not 1/2 of it. Also we only have one Fman so no need for the code to deal with a second. Signed-off-by: -
Kumar Gala authored
On CoreNet based SoCs (P2040, P3041, P4080, P5020) we have some additional rules to determining the various frequencies that PME & FMan IP blocks run at. We need to take into account: * Reduced number of Core Complex PLL clusters * HWA_ASYNC_DIV (allows for /2 or /4 options) On P2040/P3041/P5020 we only have 2 Core Complex PLLs and in such SoCs the PME & FMan blocks utilize the second Core Complex PLL. On SoCs like p4080 with 4 Core Complex PLLs we utilize the third Core Complex PLL for PME & FMan blocks. On P2040/P3041/P5020 we have the added feature that we can divide the PLL down further by either /2 or /4 based on HWA_ASYNC_DIV. On P4080 this options doesn't exist, however HWA_ASYNC_DIV field in RCW should be set to 0 and this gets a backward compatiable /2 behavior. Signed-off-by: -
Zhao Chenhui authored
MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage device support using PCI EHCI module. Signed-off-by:
-
Zhao Chenhui authored
Signed-off-by:
-
Zhao Chenhui authored
Signed-off-by:
-
Poonam Aggrwal authored
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by:
-
Poonam Aggrwal authored
Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns Signed-off-by:
-
Poonam Aggrwal authored
RevB boards never really made it outside of Freescale and have been replaced with RevC & RevD which had various board bug fixes. Signed-off-by:
-
Priyanka Jain authored
PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width. On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI] switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width. Signed-off-by:Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by:
-
Priyanka Jain authored
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by:
-
Timur Tabi authored
The NXID EEPROM format comes in two versions, v0 and v1. The only difference is in the number of MAC addresses that can be stored. NXID v0 supports eight addresses, and NXID v1 supports 23. Rather than allow a board to choose which version to support, NXID v0 is now considered deprecated. The EEPROM code is updated to support only NXID v1, but it can still read EEPROMs formatted with v0. In these cases, the EEPROM data is loaded and the CRC is verified, but the data is stored into a v1 data structure. If the EEPROM data is written back, it is written in v1 format. This allows existing v0-formatted EEPROMs to continue providing MAC addresses, but any changes to the data will force an upgrade to the v1 format, while retaining all data. Signed-off-by:
-
Kumar Gala authored
CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager. Signed-off-by: -
Priyanka Jain authored
SDHC clock is equal to CCB on P1010 and P1014 not CCB/2. Signed-off-by:
-
Poonam Aggrwal authored
Add defines for FSL_SATA_V2, # of DDR controllers, reset value of CCSRBAR and SDHC erratum. Signed-off-by:
-
Kumar Gala authored
Add Support for Freescale P1024/P1025 (dual core) and P1015/P1016 (single core) processors. P1024 is a variant of P1020 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1025 is a variant of P1021 processor with a core frequency from 400Mhz to 667Mhz and comes in a 561-pin wirebond power-BGA P1015 is a variant of P1024 processor with single core and P1016 is a variant of P1025 processor with single core. Added comments in config_mpc85xx.h to denote single core versions of processors. Signed-off-by:
Jin Qing <b24347@freescale.com> Signed-off-by:
-
