- Apr 04, 2009
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Wolfgang Denk authored
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Andreas Huber authored
On platforms with multiple NOR chips, currently only the first one can be selected using the "ubi part" command. This patch fixes this problem by using different names for the NOR "mtd devices". It also changes the name of the NOR MTD device from "cfi-mtd" to "norX" (X indexing the device numer) to better match the mtdparts defaults. Signed-off-by:
Stefan Roese <sr@denx.de> Signed-off-by:
Andreas Huber <andreas.huber@keymile.com>
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Sascha Hauer authored
Do not initialize phy on startup, instead initialize it when we actually need it. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
introduce serial_exit for this purpose. Use it only when the rm9200 serial driver is active Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
add CONFIG_AT91RM9200_USART to activate the driver Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Ulf Samuelsson authored
The AT91RM9200-EK Evaluation Board supports the AT91RM9200 ARM9-based 32-bit RISC microcontroller and enables real-time code development and evaluation. Here is the chip page on Atmel website: http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507 with - NOR (cfi driver) - DataFlash - USB OHCI - Net - I2C (hard) Signed-off-by:
Ulf Samuelsson <ulf@atmel.com> Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Kumar Gala authored
In set_ddr_laws() when we determined how much of the size requested to be mapped was covered by the the first LAW we needed to recalculate the size based on what was actually mapped. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- Apr 03, 2009
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unsik Kim authored
Mflash is fusion memory device mainly targeted consumer eletronic and mobile phone. Internally, it have nand flash and other hardware logics and supports some different operation (ATA, IO, XIP) modes. IO mode is custom mode for the host that doesn't have IDE interface. (Many mobile targeted SoC doesn't have IDE bus) This driver support mflash IO mode. Followings are brief descriptions about IO mode. 1. IO mode based on ATA protocol and uses some custom command. (read confirm, write confirm) 2. IO mode uses SRAM bus interface. Signed-off-by:
unsik Kim <donari75@gmail.com>
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Detlev Zundel authored
Fix problems introduced in commit 7b5611cd [inka4x0: Add hardware diagnosis functions for inka4x0] which redefined MSR_RI which is already used on PowerPC systems. Also eliminate redundant definitions in ps2mult.h. More cleanup will be needed for other redundant occurrences though. Signed-off-by:
Detlev Zundel <dzu@denx.de>
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Scott Wood authored
Legacy NAND is marked for feature removal after April 2009 (i.e. this upcoming release). There are still several boards that reference it (though many do so only for disk-on-chip support which has been silently disabled for a while now). These boards will now fail to build with #error, though the code is still there if the user removes #error. The plan is to remove the code outright in the next release, along with any board code that refers to it (such as board/esd/common/auto_update.c). Also, remove the legacy NAND API description from README.nand. Signed-off-by:
Scott Wood <scottwood@freescale.com>
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- Apr 02, 2009
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Mike Frysinger authored
I can't find anywhere in the datasheet that says the status register needs 3 dummy bytes sent to it before being able to read back the first real result. Tests on a Blackfin board show that after writing the opcode, the status register starts coming back immediately. So only write out the read status register opcode before polling the result. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> CC: Jason McMullan <mcmullan@netapp.com> CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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Mike Frysinger authored
Since timeouts are only hit when there is a problem in the system, we don't want to prematurely timeout on a functioning setup. Thus having low timeouts (in milliseconds) doesn't gain us anything in the production case, but rather increases likely hood of causing problems where none otherwise exist. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org> CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Mike Frysinger authored
Some SPI flash drivers like to have extended id information available (like the spansion flash), so rather than making it re-issue the ID cmd to get at the last 2 bytes, have the common code read 5 bytes rather than just 3. This also matches the Linux behavior where it always reads 5 id bytes from all flashes. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Acked-by:
Haavard Skinnemoen <haavard.skinnemoen@atmel.com> CC: Mingkai Hu <Mingkai.hu@freescale.com>
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Mike Frysinger authored
The common SPI flash code reads the idcode and passes it down to the SPI flash driver, so there is no need to read it again ourselves. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Acked-by:
Haavard Skinnemoen <haavard.skinnemoen@atmel.com> CC: Jason McMullan <mcmullan@netapp.com> CC: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Acked-by:
Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Acked-by:
Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
- AT45DB321D - AT45DB161D - AT45DB081D - AT45DB041D - AT45DB021D - AT45DB011D Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mingkai Hu authored
Add MTD SPI Flash support for S25FL008A, S25FL016A, S25FL032A, S25FL064A, S25FL128P. Signed-off-by:
Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
The Blackfin SDH controller is still using the legacy framework, so update the driver to use the renamed functions. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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- Mar 31, 2009
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Jens Scharsig authored
This patch fix the compiler/linker errors common/cmd_i2c.c:1252: undefined reference to `i2c_get_bus_speed' common/cmd_i2c.c:1256: undefined reference to `i2c_set_bus_speed' if board use CONFIG_I2C_CMD_TREE and CONFIG_I2C_MULTI_BUS is not uesd/undef (wrong define order) and removes additional empty lines Signed-off-by:
Jens Scharsig <esw@bus-elektronik.de>
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- Mar 30, 2009
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Haiying Wang authored
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Haiying Wang authored
For the silicon which doesn't have ROM support in QE, it always needs to load a pre-built ucode binary to IRAM so that QE can work. Signed-off-by:
Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by:
Hillel Avni <Hillel.Avni@freescale.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Detlev Zundel authored
Signed-off-by:
Detlev Zundel <dzu@denx.de> Signed-off-by:
Andreas Pfefferle <ap@denx.de>
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Detlev Zundel authored
This pretty unintelligent interface is used on some RTC chips. Signed-off-by:
Detlev Zundel <dzu@denx.de>
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- Mar 29, 2009
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Jean-Christophe PLAGNIOL-VILLARD authored
add CONFIG_CLPS7111_SERIAL to activate the driver Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
add CONFIG_LPC2292_SERIAL to activate the driver Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
add CONFIG_KS8695_SERIAL to activate the driver Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
add CONFIG_USB_S3C64XX to activate the driver Signed-off-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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