- Feb 05, 2019
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Troy Kisky authored
Signed-off-by:Troy Kisky <troy.kisky@boundarydevices.com>
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Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Ye Li authored
The HS400 ES (Enhanced Strobe) has been added. This patch addes support for HS400 for eMMC 5.0 devices. It needs tuning at HS200 to synchronize command response. Signed-off-by:
Ye Li <ye.li@nxp.com> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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Peng Fan authored
Add HS400 ES mode support. The flow is same as mmc_select_hs400es in kernel drivers/mmc/core/mmc.c. With HS400 ES, there is no tuning needed. With Toshiba 32GB Automotive eMMC5.1 on 8QXP ARM2 board, speed test: 'time mmc read 0x90000000 0 0x200000' shows that speed is 282MB/s. Signed-off-by:
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Peng Fan authored
Add SD/MMC legacy capability. Otherwise the legacy cards supports will be broken. Signed-off-by: -
Jean-Jacques Hiblot authored
Add a new callback function *card_busy* which can be used to check if the card is busy. This is useful during UHS voltage switching to check if the switch was successful. Not all controllers may support this, so it's optional and when not provided the card is deemed ready. Signed-off-by:Jean-Jacques Hiblot <jjhiblot@ti.com>
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Kishon Vijay Abraham I authored
Add a new callback function *set_vdd* which can be used by the platform mmc driver to enable or disable vdd. The mmc core can use *mmc_set_vdd* in order to invoke the callback function. This will be used during power cycle where the specification requires vdd to be disabled for 1ms and enabled again. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Peng Fan authored
Add compatible entry in imx8m pinctrl driver for i.MX8MM Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Ye Li authored
The SPL SDP is configured as BOOT_DEVICE_BOARD, so when booting from USB, change its type to BOOT_DEVICE_BOARD, so we can use SDP. Signed-off-by: -
Peng Fan authored
When boot type could not be detected from rom sw info, read sbmr1 to detect, here we only use it to detect FLEXSPI boot, because ROM not update it in rom sw info. Signed-off-by: -
Ye Li authored
Since the SD is usdhc2 and eMMC is usdhc3, this cause mapping problem for spl_boot_device. So far hard coded them to correct MMC index, so that SD and eMMC boot can work. Signed-off-by:
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Ye Li authored
Introduce two board level callback functions to FIT image loading process, and a SPL_FIT_FOUND flag to differentiate FIT image or RAW image. Implement functions in imx common SPL codes to call HAB funtion to authenticate the FIT image. Generally, we have to sign multiple regions in FIT image: 1. Sign FIT FDT data (configuration) 2. Sign FIT external data (Sub-images) Because the CSF supports to sign multiple memory blocks, so that we can use one signature to cover all regions in FIT image and only authenticate once. The authentication should be done after the entire FIT image is loaded into memory including all sub-images. We use "-p" option to generate FIT image to reserve a space for FIT IVT and FIT CSF, also this help to fix the offset of the external data (u-boot-nodtb.bin, ATF, u-boot DTB). The signed FIT image layout is as below: -------------------------------------------------- | | | | | | | | | FIT | FIT | FIT | | U-BOOT | ATF | U-BOOT | | FDT | IVT | CSF | | nodtb.bin | | DTB | | | | | | | | | -------------------------------------------------- Signed-off-by:
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Ye Li authored
Enable the CONFIG_SUPPORT_EMMC_BOOT, so that for eMMC boot SPL can switch to boot partition for u-boot.img loading. Signed-off-by:
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Ye Li authored
Since we don't support DM in SPL, undefine the DM USB in SPL build, so it can use non-DM USB driver. Signed-off-by: -
Troy Kisky authored
Signed-off-by: -
Ye Li authored
The board_usb_clean in ehci-mx6 always set to HOST. This is wrong when we running gadget. Change to use type in private data. Signed-off-by: -
Ye Li authored
Since the i.MX8MM reuses the otg controllers on i.MX7D. We can use CONFIG_USB_EHCI_MX7 for them. Due the TCPC and load switch are used on Typec circuit. Add the board_usb_init and board_usb_cleanup to ehci-mx6 DM driver. So we can implement the TCPC settings in these board functions. Signed-off-by: -
Ye Li authored
Since there is no uclass for USB PHY. The device won't be setup for the USB PHY node in DTB. And its associated power domain device won't be turned on neither by DM framework. This patch modifies the ehci-mx6 driver to enable the power domain device before access the USB PHY. This is only for DM driver. For non-DM part, users still need to power on the USB PHY in boards/SoC codes. Signed-off-by:
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Ye Li authored
The i.MX8 has two USB controllers: USBOH and USB3. The USBOH reuses previous i.MX6/7. It has same PHY IP as i.MX7ULP but NC registers are same as i.MX7D. So add its support in ehci-mx6 driver. Also the driver is updated to remove build warning for 64 bits CPU. Signed-off-by: -
Ye Li authored
The i.MX7ulp EVK board uses GPIO to detect ID for USB OTG0, but when using DM USB driver, it is hard coded to use OTG ID pin. Add a board override function that when extcon property is provided, the function can check the GPIO to get ID. Signed-off-by: -
Ye Li authored
When doing port reset, the PR bit of PORTSC1 will be automatically cleared by our IP, but standard EHCI needs explicit clear by software. The EHCI-HCD driver follow the EHCI specification, so after 50ms wait, it clear the PR bit by writting to the PORTSC1 register with value loaded before setting PR. This sequence is ok for our IP when the delay time is exact. But when the timer is slower, some bits like PE, PSPD have been set by controller automatically after the PR is automatically cleared. So the writing to the PORTSC1 will overwrite these bits set by controller. And eventually the driver gets wrong status. We implement the powerup_fixup operation which delays 50ms and will check the PR until it is cleared by controller. And will update the reg value which is written to PORTSC register by EHCI-HCD driver. This is much safer than depending on the delay time to be accurate and aligining with controller's behaiver. Signed-off-by: -
Ye Li authored
The ULP has two USB controllers. These two controllers have similar NC registers layout as i.MX7D. But OTG0 uses UTMI PHY simliar as i.MX6, not the integrated PHY on i.MX7D. The OTG1 needs off-chip HSIC PHY or ULPI PHY to work. This patch only supports OTG0 with UTMI PHY. Signed-off-by: -
Ye Li authored
Add the fuse checking in drivers, when the module is disabled in fuse, the driver will not work. Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C, USB-EHCI, GIS, LCDIF. Signed-off-by: -
Fugang Duan authored
From i2c spec, if device pull down the SDA line that causes i2c bus dead, host can send out 9 clock to let device release SDA. But for some special device like pfuze100, it pull down SDA line and the solution cannot take effort. The patch just add NACK and STOP signal after 8 dummy clock, and pmic can release SDA line after the recovery. Test case catch 375 times of i2c hang, and all are recovered. Signed-off-by:
Fugang Duan <B38611@freescale.com> (cherry picked from commit 53118db42d201d36ca9067b4bb0e2702399e100b) Signed-off-by:
Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit b8dcb812401026cb2189b24a4f6058830151c85a) (cherry picked from commit c5a44a2a0b2218221cb12645b10f0b34ecc6f79b)
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