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  1. Jan 18, 2017
  2. Jan 05, 2017
  3. Dec 16, 2016
  4. Dec 09, 2016
    • Patrick Delaunay's avatar
      arm: armv7: add us timer for bootstage · 91558c81
      Patrick Delaunay authored
      
      solve issue when bootstage is used with armV7 generic timer
      first call of timer_get_boot_us() use the function get_timer()
      before timer initialization (arch.timer_rate_hz = 0)
      => div by 0
      
      Commit-notes
      
      When I activate bootstage on ARMV7 architecture with platform
      using the generic armv7 timer defined in file
      ./arch/arm/cpu/armv7m/timer.c
      
      I have a issue because gd->arch.timer_rate_hz = 0
      
      For me the get_timer() function should not used before timer_init
      (which initialize gd->arch.timer_rate_hz) at least for the ARMV7
      timer.
      
      But in the init sequence, the first bootstage fucntion is called
      before timer_init and this function use the timer function.
      
      For me it is a error in the generic init sequence :
      mark_bootstage is called before timer_init.
      
      static init_fnc_t init_sequence_f[] = {
      ....
          arch_cpu_init_dm,
          mark_bootstage,        /* need timer, go after init dm */
      ...
      #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
              defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \
              defined(CONFIG_SPARC)
          timer_init,        /* initialize timer */
      #endif
      .......
      
      To solve the issue for all the paltform, we can move timer_init()
      call just before mark_bootstage() in this array...
      
      It should be ok for ARMV7 but I don't sure for other platform
      impacted
      - the other ARM platform or ARMV7 wich don't use generic timer
      - MIPS BLACKFIN NDS32 or SPARC
      
      and I don't sure of impact for other function called
      (board_early_init_f for example....)
      
      => This patch solve issue only in timer armv7
         get_boot_us() can be called everytime without div by 0 issue
         (gd->arch.timer_rate_hz is not used)
      
      END
      
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay@st.com>
      Signed-off-by: default avatarPatrick Delaunay <patrick.delaunay73@gmail.com>
      91558c81
  5. Dec 02, 2016
  6. Nov 30, 2016
  7. Nov 29, 2016
    • Breno Lima's avatar
      mx6sx: Add initial support for UDOO Neo Board · 792f1868
      Breno Lima authored
      UDOO Neo Board is a development board from Seco that has three models:
       - UDOO Neo Basic
       - UDOO Neo Basic Kick Starter
       - UDOO Neo Extended
       - UDOO Neo Full
      
      All versions are based on the i.MX6 SoloX processor.
      
      For more details about the UDOO Neo board, please refer to:
      http://www.udoo.org/udoo-neo/
      
      This work is based on a previous commit of Francesco Montefoschi
      <francesco.monte@gmail.com>:
      https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844
      
      
      
      Only tested on the UDOO Neo Full board.
      
      Signed-off-by: default avatarBreno Lima <breno.lima@nxp.com>
      Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      792f1868
    • Eric Nelson's avatar
      ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines · a425bf72
      Eric Nelson authored
      
      The DDR calibration routines are gated by conditionals for the
      i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
      are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
      
      Also, since only the Novena board currently uses the dynamic
      DDR calibration routines, these routines waste space on other
      boards using SPL.
      
      Add a KConfig entry to allow boards to selectively include the
      DDR calibration routines.
      
      Signed-off-by: default avatarEric Nelson <eric@nelint.com>
      a425bf72
    • Eric Nelson's avatar
      mx6: ddr: add routine to return DDR calibration data · 48c7d437
      Eric Nelson authored
      
      Add routine mmdc_read_calibration() to return the output of DDR
      calibration. This can be used for debugging or to aid in construction
      of static memory configuration.
      
      This routine will be used in a subsequent patch set adding a virtual
      "mx6memcal" board, but could also be useful when gathering statistics
      during an initial production run.
      
      Signed-off-by: default avatarEric Nelson <eric@nelint.com>
      48c7d437
    • Eric Nelson's avatar
      mx6: ddr: pass mx6_ddr_sysinfo to calibration routines · 7f17fb74
      Eric Nelson authored
      
      The DDR calibration routines have scattered support for bus
      widths other than 64-bits:
      
      -- The mmdc_do_write_level_calibration() routine assumes the
      presence of PHY1, and
      -- The mmdc_do_dqs_calibration() routine tries to determine
      whether one or two DDR PHYs are active by reading MDCTL.
      
      Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
      for use in calling mx6_dram_cfg(), and the bus width is available in the
      "dsize" field, use this structure to inform the calibration routines which
      PHYs are active.
      
      This allows the use of the DDR calibration routines on CPU variants
      like i.MX6SL that only have a single MMDC port.
      
      Signed-off-by: default avatarEric Nelson <eric@nelint.com>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
      7f17fb74
    • Eric Nelson's avatar
      mx6: ddr: allow 32 cycles for DQS gating calibration · b33f74ea
      Eric Nelson authored
      
      The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
      cycle) for the first PHY.
      
      Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
      output value isn't polluted with calibration artifacts.
      
      Signed-off-by: default avatarEric Nelson <eric@nelint.com>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
      b33f74ea
    • Peng Fan's avatar
      armv7: psci: cpu_off: flush D-Cache before disable D-Cache · fea7452c
      Peng Fan authored
      
      Before disable cache, need to first flush cache.
      
      There maybe dirty data in D-Cache before disable D-Cache.
      After disable D-Cache, the first store instructions in
      psci_v7_flush_dcache_all will directly store registers
      {r4-r5, r7, r9-r11, lr} to memory.
      If there is dirty data before disable D-Cache,
      psci_v7_flush_dcache_all will flush data to memory,
      and may overwrite the memory that hold the registers
      {r4-r5, r7, r9-r11, lr}.
      
      So before disable cache, first flush D-Cache.
      
      Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
      Cc: Albert Aribaud <albert.u.boot@aribaud.net>
      Cc: Chen-Yu Tsai <wens@csie.org>
      Cc: Hans de Goede <hdegoede@redhat.com>
      Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
      Cc: York Sun <york.sun@nxp.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Tom Rini <trini@konsulko.com>
      fea7452c
  8. Nov 21, 2016
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