- Jan 18, 2017
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Hou Zhiqiang authored
Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
York Sun <york.sun@nxp.com>
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- Jan 05, 2017
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York Sun authored
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by:
York Sun <york.sun@nxp.com>
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York Sun authored
Use Kconfig to select errata workaround. Signed-off-by:
York Sun <york.sun@nxp.com>
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York Sun authored
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by:
York Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by:
Tom Rini <trini@konsulko.com>
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York Sun authored
Use Kconfig option to set little- or big-endian access to secure boot and trust architecture. Signed-off-by:
York Sun <york.sun@nxp.com>
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York Sun authored
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC and ARM SoCs, move it to Kconfig under the driver. Signed-off-by:
York Sun <york.sun@nxp.com>
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- Dec 16, 2016
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Jagan Teki authored
Add FEC support for Engicam i.CoreM6 RQS modules. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Jagan Teki authored
Add FEC support for Engicam GEAM6UL module. Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Jagan Teki authored
Add I2C support for Engicam i.CoreM6 RQS modules. icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl-rqs> i2c dev 0 Setting bus to 0 icorem6qdl-rqs> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl-rqs> i2c probe Valid chip addresses: 4F icorem6qdl-rqs> i2c md 4F 0xff 00ff: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ icorem6qdl-rqs> i2c bus Bus 0: i2c@021a0000 (active 0) 4f: generic_4f, offset len 1, flags 0 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Jagan Teki authored
Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1 U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530) CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Jagan Teki authored
Add I2C support for Engicam GEAM6UL module. geam6ul> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 geam6ul> i2c dev 0 Setting bus to 0 geam6ul> i2c dev Current bus is 0 geam6ul> i2c speed 100000 Setting bus speed to 100000 Hz geam6ul> i2c probe Valid chip addresses: 2C geam6ul> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Jagan Teki authored
Boot Log: -------- U-Boot SPL 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30) Trying to boot from MMC1 U-Boot 2016.11-rc2-00144-g922adaa-dirty (Oct 28 2016 - 18:55:30 +0530) CPU: Freescale i.MX6UL rev1.1 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 43C Reset cause: POR Model: Engicam GEAM6UL DRAM: 128 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 geam6ul> Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Jagan Teki authored
Add I2C support for Engicam i.CoreM6 qdl board. icorem6qdl> i2c bus Bus 0: i2c@021a0000 Bus 1: i2c@021a4000 Bus 2: i2c@021a8000 icorem6qdl> i2c dev 2 Setting bus to 2 icorem6qdl> i2c speed 100000 Setting bus speed to 100000 Hz icorem6qdl> i2c probe Valid chip addresses: 2C icorem6qdl> i2c md 2C 0xff 00ff: 00 00 00 00 0f f0 01 64 ff ff 00 00 00 00 00 00 .......d........ Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Acked-by:
Heiko Schocher <hs@denx.de>
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Jagan Teki authored
Use CONFIG_DM_ETH and remove board_eth_init code from board files. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com>
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Patrick Bruenn authored
Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices. The CX9020 differs from i.MX53 Quick Start Board by: - use uart2 instead of uart1 - DVI-D connector instead of VGA - no audio - CCAT FPGA connected to emi - enable rtc Signed-off-by:
Patrick Bruenn <p.bruenn@beckhoff.com>
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Peng Fan authored
Add i.MX6SLL EVK board support. 1. Add imx6sll-evk device tree. 2. Enable SDHC/I2C/UART. 3. Enable REGULATOR/PMIC/I2C/GPIO/SDHC/PINCTRL driver. Boot Log: U-Boot 2016.11-00127-gc635871-dirty (Nov 24 2016 - 13:28:19 +0800) CPU: Freescale i.MX6SLL rev1.0 at 792MHz CPU: Commercial temperature grade (0C to 95C)Reset cause: POR Model: Freescale i.MX6SLL EVK Board Board: MX6SLL EVK DRAM: 2 GiB i2c bus 0 at 35258368, no gpio pinctrl state. PMIC: PFUZE100! DEV_ID=0x10 REV_ID=0x21 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Peng Fan authored
add Kconfig entry for i.MX6SLL Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Peng Fan authored
Add clock support for i.MX6SLL. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Peng Fan authored
The LCDIF Pixel clock mux is not glitchless, so need to gate before changing mux. Also change enable_lcdif_clock prototype with a new input parameter to indicate disable or enable. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Peng Fan authored
Add lcdif clock support for i.MX6SL. Signed-off-by:
Peng Fan <peng.fan@nxp.com>
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Peng Fan authored
The mux for the lcd clock is not glitchless, so need to first gate the clock before changing the mux. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Peng Fan authored
>From RM, per_periph2_clk_sel option3 is: "derive clock from 198MHz clock (divided 392MHz PLL2 PFD)." So fix it. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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Marcin Niestroj authored
liteBoard is a development board which uses liteSOM as its base. Hardware specification: * liteSOM (i.MX6UL, DRAM, eMMC) * Ethernet PHY (id 0) * USB host (usb_otg1) * MicroSD slot (uSDHC1) Signed-off-by:
Marcin Niestroj <m.niestroj@grinn-global.com>
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Breno Lima authored
Add thermal support on the Kconfig file. Signed-off-by:
Breno Lima <breno.lima@nxp.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Breno Lima authored
It's not necessary to define the processor in the defconfig file. The preferred method to select the SoC is via Kconfig file. Signed-off-by:
Breno Lima <breno.lima@nxp.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Max Krummenacher authored
This adds board support for the Toradex module family Colibri iMX6. The familiy consists of a module with i.MX6 DualLite, i.MX6 Solo, both with a version for commercial and industrial temperature range. Signed-off-by:
Max Krummenacher <max.krummenacher@toradex.com>
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Max Krummenacher authored
This adds board support for the Toradex module family Apalis iMX6. The familiy consists of a module with i.MX6 Dual, i.MX6 Quad with commercial and industrial temperature range. Signed-off-by:
Max Krummenacher <max.krummenacher@toradex.com>
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- Dec 09, 2016
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Patrick Delaunay authored
solve issue when bootstage is used with armV7 generic timer first call of timer_get_boot_us() use the function get_timer() before timer initialization (arch.timer_rate_hz = 0) => div by 0 Commit-notes When I activate bootstage on ARMV7 architecture with platform using the generic armv7 timer defined in file ./arch/arm/cpu/armv7m/timer.c I have a issue because gd->arch.timer_rate_hz = 0 For me the get_timer() function should not used before timer_init (which initialize gd->arch.timer_rate_hz) at least for the ARMV7 timer. But in the init sequence, the first bootstage fucntion is called before timer_init and this function use the timer function. For me it is a error in the generic init sequence : mark_bootstage is called before timer_init. static init_fnc_t init_sequence_f[] = { .... arch_cpu_init_dm, mark_bootstage, /* need timer, go after init dm */ ... #if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \ defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32) || \ defined(CONFIG_SPARC) timer_init, /* initialize timer */ #endif ....... To solve the issue for all the paltform, we can move timer_init() call just before mark_bootstage() in this array... It should be ok for ARMV7 but I don't sure for other platform impacted - the other ARM platform or ARMV7 wich don't use generic timer - MIPS BLACKFIN NDS32 or SPARC and I don't sure of impact for other function called (board_early_init_f for example....) => This patch solve issue only in timer armv7 get_boot_us() can be called everytime without div by 0 issue (gd->arch.timer_rate_hz is not used) END Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by:
Patrick Delaunay <patrick.delaunay73@gmail.com>
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- Dec 02, 2016
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York Sun authored
Move from CONFIG_SYS_EXTRA_OPTIONS to Kconfig option. Signed-off-by:
York Sun <york.sun@nxp.com>
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- Nov 30, 2016
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Lukasz Majewski authored
This patch extends the imx6 clock code to enable or disable the EIM slow clock, which in necessary when one wants to use EIM interface t o read/write from external memory (e.g. NOR). Signed-off-by:
Lukasz Majewski <l.majewski@majess.pl>
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Christoph Fritz authored
This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by:
Christoph Fritz <chf.fritz@googlemail.com> Reviewed-by:
Stefano Babic <sbabic@denx.de> Acked-by:
Marek Vasut <marex@denx.de>
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- Nov 29, 2016
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Breno Lima authored
UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi <francesco.monte@gmail.com>: https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by:
Breno Lima <breno.lima@nxp.com> Reviewed-by:
Fabio Estevam <fabio.estevam@nxp.com>
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Eric Nelson authored
The DDR calibration routines are gated by conditionals for the i.MX6DQ SOCs, but with the use of the sysinfo parameter, these are usable on at least i.MX6SDL and i.MX6SL variants with DDR3. Also, since only the Novena board currently uses the dynamic DDR calibration routines, these routines waste space on other boards using SPL. Add a KConfig entry to allow boards to selectively include the DDR calibration routines. Signed-off-by:
Eric Nelson <eric@nelint.com>
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Eric Nelson authored
Add routine mmdc_read_calibration() to return the output of DDR calibration. This can be used for debugging or to aid in construction of static memory configuration. This routine will be used in a subsequent patch set adding a virtual "mx6memcal" board, but could also be useful when gathering statistics during an initial production run. Signed-off-by:
Eric Nelson <eric@nelint.com>
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Eric Nelson authored
The DDR calibration routines have scattered support for bus widths other than 64-bits: -- The mmdc_do_write_level_calibration() routine assumes the presence of PHY1, and -- The mmdc_do_dqs_calibration() routine tries to determine whether one or two DDR PHYs are active by reading MDCTL. Since a caller of these routines must have a valid struct mx6_ddr_sysinfo for use in calling mx6_dram_cfg(), and the bus width is available in the "dsize" field, use this structure to inform the calibration routines which PHYs are active. This allows the use of the DDR calibration routines on CPU variants like i.MX6SL that only have a single MMDC port. Signed-off-by:
Eric Nelson <eric@nelint.com> Reviewed-by:
Marek Vasut <marex@denx.de>
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Eric Nelson authored
The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample cycle) for the first PHY. Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0 output value isn't polluted with calibration artifacts. Signed-off-by:
Eric Nelson <eric@nelint.com> Reviewed-by:
Marek Vasut <marex@denx.de>
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Peng Fan authored
Before disable cache, need to first flush cache. There maybe dirty data in D-Cache before disable D-Cache. After disable D-Cache, the first store instructions in psci_v7_flush_dcache_all will directly store registers {r4-r5, r7, r9-r11, lr} to memory. If there is dirty data before disable D-Cache, psci_v7_flush_dcache_all will flush data to memory, and may overwrite the memory that hold the registers {r4-r5, r7, r9-r11, lr}. So before disable cache, first flush D-Cache. Signed-off-by:
Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: York Sun <york.sun@nxp.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Tom Rini <trini@konsulko.com>
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- Nov 21, 2016
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Tom Rini authored
This moves what was in arch/arm/cpu/armv7/omap-common in to arch/arm/mach-omap2 and moves arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2 as subdirectories. All refernces to the former locations are updated to the current locations. For the logic to decide what our outputs are, consolidate the tests into a single config.mk rather than including 4. Signed-off-by:
Tom Rini <trini@konsulko.com>
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Lokesh Vutla authored
Detect the board very early and avoid reading eeprom multiple times. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Lokesh Vutla authored
This is similar to Commit 93e6253d ("ARM: OMAP4/5: Centralize early clock initialization") that was done for OMAP4+, reflecting the same for AM33xx and AM43xx SoCs to centralize clock initialization. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> [trini: Add setup_early_clocks that calls setup_clocks_for_console for ti81xx] Signed-off-by:
Tom Rini <trini@konsulko.com>
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