- May 17, 2010
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Ron Madrid authored
This patch sets the SICRL_LBC bits in SICRL to change the function of the associated pins to GPIO functionality. Signed-off-by:
Ron Madrid <ron_madrid@sbcglobal.net>
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Kim Phillips authored
commit 167cdad1 "SERIAL: Enable port-mapped access" inadvertently broke 83xx nand boards by converting NS16550_init to use io accessors, which expanded the size of the generated code. this patch fixes the problem by removing icache functions from the nand builds, which somewhat follows commit 1a2e203b "mpc83xx: turn on icache in core initialization to improve u-boot boot time" Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Ron Madrid authored
This patch removes the checkboard function from the build of the 4k bootstrap section for the SIMPC8313 as it is not needed in the spl build. This will allow > 100 bytes of extra room for other uses. Signed-off-by:
Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Matthias Fuchs authored
Due to some overlapping sections it's time to update TEXT_BASE for this board. Signed-off-by:
Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by:
Stefan Roese <sr@denx.de>
- May 16, 2010
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de>
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- May 15, 2010
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Wolfgang Denk authored
Fix MVBLM7 and MVSMR Makefiles for correct out-of-tree building (create "bootscript.img" in build directory instead of source directory) and cleanup (remove "bootscript.img" when cleaning up). Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Andre Schwarz <andre.schwarz@matrix-vision.de>
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Wolfgang Denk authored
Signed-off-by:
Wolfgang Denk <wd@denx.de> Tested-by:
Thomas Weber <weber@corscience.de>
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Wolfgang Denk authored
Commit 77c1458d caused the following compiler warnings: fsl_esdhc.c: In function 'esdhc_pio_read_write': fsl_esdhc.c:142: warning: assignment discards qualifiers from pointer target type fsl_esdhc.c: In function 'esdhc_setup_data': fsl_esdhc.c:169: warning: unused variable 'wml_value' fsl_esdhc.c: In function 'esdhc_pio_read_write': fsl_esdhc.c:164: warning: control reaches end of non-void function Fix these. Signed-off-by:
Wolfgang Denk <wd@denx.de> Cc: Dipen Dudhat <dipen.dudhat@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
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- May 12, 2010
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York Sun authored
SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. The difference has ben examined and the code is compatible. Speed bins is not verified on hardware for CL7 at this moment. This patch also enables SPD Rev 1.x where x is up to "F". According to SPD spec, the lower nibble is optionally used to determine which additinal bytes or attribute bits have been defined. Software can safely use defaults. However, the upper nibble should always be checked. Signed-off-by:
York Sun <yorksun@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code. Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Kumar Gala authored
Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Jerry Huang authored
Using PPC I/O accessor to DIU I/O space instead of directly read/write. It will prevent the dozen of compiler order issue and PPC hardware order issue for accessing I/O space. Using the toolchain(tc-fsl-x86lnx-e500-dp-4.3.74-2.i386.rpm) can show up the order issue of DIU driver. Signed-off-by:
Dave Liu <daveliu@freescale.com> Signed-off-by:
Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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- May 08, 2010
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- May 07, 2010
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Andre Schwarz authored
Add USB commands. Rename autoscript to bootscript. Add automatic bootscript image generation to makefile. Signed-off-by:
Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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Ron Madrid authored
Added UPM array table, upmconfig, and Local Bus configuration support for SIMPC8313 Signed-off-by:
Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by:
Kim Phillips <kim.phillips@freescale.com>
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- May 06, 2010
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Mike Frysinger authored
Only one file apparently defines this function, and it merely stubs it out. So if no one is defining/calling it, punt it. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
With the cpu include paths moved, the gitignore paths need updating. Signed-off-by:
Mike Frysinger <vapier@gentoo.org> Tested-by:
Tom Rix <tom@bumblecow.com>
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Kumar Gala authored
When we changed ARCH from ppc to powerpc we need to treat HOSTARCH the same way. We use HOSTARCH == ARCH to determine if a build is native. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Serge Ziryukin authored
Signed-off-by:
Serge Ziryukin <ftrvxmtrx@gmail.com>
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Stefan Roese authored
This patch consolidates bootcount_{store|load} for PowerPC by implementing a common version in arch/powerpc/lib/bootcount.c. This code is now used by all PowerPC variants that currently have these functions implemented. The functions now use the proper IO-accessor functions to read/write the values. This code also supports two different bootcount versions: a) Use 2 separate words (2 * 32bit) to store the bootcounter b) Use only 1 word (2 * 16bit) to store the bootcounter Version b) was already used by MPC5xxx. Signed-off-by:
Stefan Roese <sr@denx.de> Acked-by:
Detlev Zundel <dzu@denx.de> Acked-by:
Kim Phillips <kim.phillips@freescale.com> for 83xx parts Cc: Michael Zaidman <michael.zaidman@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: Anatolij Gustschin <agust@denx.de>
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- May 05, 2010
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Ender.Dai authored
Fix conditional compile rule for twl4030.c and videomodes.c. Signed-off-by:
Ender.Dai <ender.dai@gmail.com>
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Larry Johnson authored
Signed-off-by:
Larry Johnson <lrj@acm.org>
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Mike Frysinger authored
Recent crc changes started using the "uint" type in headers that are used on the build system. This subsequently broke mingw targets as they do not provide such a type. So add this basic typedef to compiler.h so that we do not have to worry about this breaking again in the future. Signed-off-by:
Mike Frysinger <vapier@gentoo.org>
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Trübenbach, Ralf authored
Enable the auto completion (with TAB) of the environment variable name after the editenv command. Signed-off-by:
Ralf Trübenbach <ralf.truebenbach@men.de>
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Reinhard Arlt authored
Add ECC support for DDR RAM for MV64360 on esd CPCI-CPU/750 board. This patch also adds the "pldver" command to display the CPLD revision. Signed-off-by:
Reinhard Arlt <reinhard.arlt@esd.eu> Signed-off-by:
Stefan Roese <sr@denx.de>
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Graeme Russ authored
Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
AMD recently changed the licensing of the RAM sizing code to the GPLv2 (or at your option any later version) Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
The eNET uses the sc520 software timers rather than the PC/AT clones Set all interrupts and timers up to be PC/AT compatible Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
The clock interupt has always been 1kHz as per timer_init() in /arch/i386/cpu/sc520/sc520_timer.c Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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Graeme Russ authored
Onboard AMD Flash chip does not support buffered writes Signed-off-by:
Graeme Russ <graeme.russ@gmail.com>
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