We may want to run different firmware before running U-Boot.  For
example, ARM Trusted Firmware runs before U-Boot, making U-Boot
a non-secure world boot loader.  In this case, the SoC might be
initialized there, which enables us to skip SPL entirely.

This commit removes "select SPL" to make it configurable.  This
also enables the Multi SoC support for the UniPhier ARMv8 SoCs.
(CONFIG_ARCH_UNIPHIER_V8_MULTI)  Thanks to the driver model and
Device Tree, the U-Boot proper part is now written in a generic way.
The board/SoC parameters reside in DT.  The Multi SoC support
increases the memory footprint a bit, but the U-Boot proper does
not have strict memory constraint.  This will mitigate the per-SoC
(sometimes per-board) defconfig burden.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

We have long had available optimized versions of the memset and memcpy
functions that are borrowed from the Linux kernel.  We should use these
in normal conditions as the speed wins in many workflows outweigh the
relatively minor size increase.  However, we have a number of places
where we're simply too close to size limits in SPL and must be able to
make the size vs performance trade-off in those cases.

Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1]
Signed-off-by: Tom Rini <trini@konsulko.com>

Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.

Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>

Use Kconfig option to set little- or big-endian access to secure
boot and trust architecture.

Signed-off-by: York Sun <york.sun@nxp.com>

Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.

Signed-off-by: York Sun <york.sun@nxp.com>

Commit be72591b ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
Kconfig") is misconversion.

The original logic in include/configs/uniphier.h was as follows:

  #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
  #define CONFIG_USE_ARCH_MEMSET
  #define CONFIG_USE_ARCH_MEMCPY
  #endif

This means those configs were enabled when building U-Boot proper,
but disabled when building SPL.  Likewise for Tegra.

Now "depends on !SPL" prevents any boards with SPL support
from reaching these options.  This changed the behavior for
UniPhier and Tegra SoC family.

Please notice these two options only control the U-Boot proper
build.  As you see arch/arm/Makefile, ARM-specific memset/memcpy
are never compiled for SPL.  So, __HAVE_ARCH_MEMCPY/MEMSET should
not set for SPL.

Fixes: be72591b ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Move USE_ARCH_MEMCPY/MEMSET options to Kconfig.

Make it "default y" for the ARMv7 architecture and make it
depend on !ARM64 && !SPL.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>

liteSOM is a System On Module (http://grinn-global.com/litesom/

). It
can't exists on its own, but will be used as part of other boards.

Hardware specification:
 * NXP i.MX6UL processor
 * 256M or 512M DDR3 memory
 * optional eMMC (uSDHC2)

Here we treat SOM similar to SOC, so we place it inside arch/arm/mach-*
directory and make it possible to reuse initialization code (i.e. DDR,
eMMC init) for all boards that use it.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>

This is a user configurable option, but "select BLK" forces users to
enable it.

Even with this commit, BLK is still enabled by "default y if DM_MMC"
for UniPhier SoCs; the difference is users can disable it if they
do not need it.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Valid Altera SoCFPGA preloader image must contain special data at
offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
0x50. These addresses are by default used by U-Boot's vector table
and a piece of reset handler, thus a valid preloader corrupts those
addresses slightly. While this works most of the time, this can and
does prevent the board from rebooting sometimes and triggering this
issue may even depend on compiler.

The problem is that when SoCFPGA performs warm reset, it checks the
addresses 0x40..0x4b in SRAM for a valid preloader signature and
header checksum. If those are found, it jumps to address 0x4c or
0x50 (this is unclear). These addresses are populated by the first
few instructions of arch/arm/cpu/armv7/start.S:

ffff0040 <data_abort>:
ffff0040:       ebfffffe        bl      ffff0040 <data_abort>

ffff0044 <reset>:
ffff0044:       ea000012        b       ffff0094 <save_boot_params>

ffff0048 <save_boot_params_ret>:
ffff0048:       e10f0000        mrs     r0, CPSR
ffff004c:       e200101f        and     r1, r0, #31
ffff0050:       e331001a        teq     r1, #26

Without this patch, the CPU will enter the code at 0xffff004c or
0xffff0050 , at which point the value of r0 and r1 registers is
undefined. Moreover, jumping directly to the preloader entry point
at address 0xffff0000 will also fail, because address 0xffff004.
is invalid and contains the preloader magic.

Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
populates offset 0x50 with jump to the entry point. This way, the
preloader signature is stored in reserved space and can not corrupt
the SPL code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Stefan Roese <sr@denx.de>
Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com>

These are the last two samsung boards that don't use DM_I2C. Move them
over, leaving #ifdefs to allow the maintainer to complete this work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>

Three boards are still not converting to use DM_I2C. They are also using
the old PMIC framework. Rather than removing them, add #ifdefs to allow
them to continue to build. This will give the maintainers a little more
time to decide whether to convert them or not.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>

This board has not been converted to DM_SERIAL by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: David Müller <d.mueller@elsoft.ch>
Reviewed-by: Jagan Teki <jagan@openedev.com>

This board has not been converted to DM_SERIAL by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: David Müller <d.mueller@elsoft.ch>

This commit adds basic support including:
MMC, Serial console

Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

This patch removes use of U_BOOT_DEVICE in board/raspberrypi/rpi/rpi.c,
enables OF_CONTROL in the config and adjusts the rpi_*defconfig configs.

Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Currently, USB is forced-enabled for the sunxi familly, and there is no
way to disable it.

However, USB takes a long time to initiliase, delaying the boot by up to
5 seconds (without any USB device attached!). This is a very long delay,
especially in cases where USB booting is not wanted at all, and where
the device is expected to boot relatively often (even in production).

Change the way the dependencies are handled, by only forcibly selecting
USB when CONFIG_DISTRO_DEFAULTS ("defaults suitable for booting general
purpose Linux distributions") is set. This option defaults to y for the
sunxi familly, so the current default behaviour is kept unchanged. Users
interested in boot time and/or size will be able to disable this to
further disable USB.

With USB disabled, the time spent in U-Boot before handing control to
the Linux kernel is about 1s now, down from ~5s (Nanopi Neo, sunxi H3).

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans De Goede <hdegoede@redhat.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

To support loading a 32-bit OS, the execution state will change from
AArch64 to AArch32 when jumping to kernel.

The architecture information will be got through checking FIT image,
then U-Boot will load 32-bit OS or 64-bit OS automatically.

Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories.  All refernces to the former locations are updated to
the current locations.  For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.

Signed-off-by: Tom Rini <trini@konsulko.com>

To start consolidating various TI-related code, introduce the ARCH_OMAP2
symbol.  While we have removed omap2-specific boards some time ago,
matching up with the kernel naming here will help overall.

Signed-off-by: Tom Rini <trini@konsulko.com>

The patch adds support for Freescale ls1021a-iot board.

Signed-off-by: Feng Li <feng.li_2@nxp.com>
[YS: rewrite commit message, fix whitespace in Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>

This is the initial commit for UniPhier reset controller driver.
Most code was ported from Linux.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.

Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Following commits 217f92bb and 15446988, these two config
CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig,
for correctly select ARMV7_PSCI.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.

This is similar to what has already been done in
9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Enable DM_PWM and DM_REGULATOR on rockchip SoCs.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

Compared to the Armada 3700, the Armada 7K and 8K are much more on the
high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as
opposed to the Cortex-A53 for the Armada 3700.

The Armada 7K and 8K also use a fairly unique architecture, internally
they are composed of several components:

- One AP (Application Processor), which contains the processor itself
  and a few core hardware blocks. The AP used in the Armada 7K and 8K
  is called AP806, and is available in two configurations:
  dual Cortex-A72 and quad Cortex-A72.
- One or two CP (Communication Processor), which contain most of the I/O
  interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one
  CP, while the 8K family chips integrate two CPs, providing two times
  the number of I/O interfaces available in the CP.
  The CP used in the 7K and 8K is called CP110.

All in all, this gives the following combinations:

- Armada 7020, which is a dual Cortex-A72 with one CP
- Armada 7040, which is a quad Cortex-A72 with one CP
- Armada 8020, which is a dual Cortex-A72 with two CPs
- Armada 8040, which is a quad Cortex-A72 with two CPs

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support,
starting with the Marvell DB-88F7040 development board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>

The Armada 3700 integrates the following interfaces (not complete list):
- Dual Cortex-A53 ARMv8
- USB 3.0
- SATA 3.0
- PCIe 2.0
- 2 x Gigabit Ethernet 1Gbps / 2.5Gbps
- ...

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support
for the Marvell DB-88F3720 development board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Wilson Ding <dingwei@marvell.com>
Cc: Victor Gu <xigu@marvell.com>
Cc: Hua Jing <jinghua@marvell.com>
Cc: Terry Zhou <bjzhou@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Cc: Haim Boot <hayim@marvell.com>

Move this option to Kconfig and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Move this option to Kconfig and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Move this config to Kconfig option and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Calvin Johnson <calvin.johnson@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Move this option to Kconfig and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Mingkai Hu <mingkai.hu@nxp.com>
CC: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

As I repeated in the ML, I am unhappy with config entries with bare
defaults.  Kick them out of arch/arm/mach-uniphier/Kconfig.

Currently, CONFIG_SPL_SERIAL_SUPPORT is not user-configurable
(build fails without it), but it should be fixed later anyway,
so I am moving CONFIG_SPL_SERIAL_SUPPORT to defconfigs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Select DM_USB to compatible with USB DM driver model.

Signed-off-by: MengDongyang <daniel.meng@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>

Now all UniPhier SoCs support a pinctrl driver.  Select (SPL_)PINCTRL
since it is mandatory even for base use.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

LS1046AQDS Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe: supports Gen 1 and Gen 2

SATA 3.0: one SATA 3.0 port

USB 3.0: two micro AB connector and one type A connector

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

LS1046ARDB Specification:
-------------------------
Memory subsystem:
 * 8GByte DDR4 SDRAM (64bit bus)
 * 512 Mbyte NAND flash
 * Two 64 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card
 * On-board 4G eMMC

Ethernet:
 * Two XFI 10G ports
 * Two SGMII ports
 * Two RGMII ports

PCIe:
 * PCIe1 (SerDes2 Lane0) to miniPCIe slot
 * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
 * PCIe3 (SerDes2 Lane2) to x4 PCIe slot

SATA:
 * SerDes2 Lane3 to SATA port

USB 3.0: one super speed USB 3.0 type A port
	 one Micro-AB port

UART: supports two UARTs up to 115200 bps for console

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>