Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
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Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>

This is used by both powerpc and arm, but I think it still qualifies as
architecture-specific.

Signed-off-by: Simon Glass <sjg@chromium.org>

The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.

Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>

Up now only MX5 and MX6 can share code, because they have
a common source directory in cpu/armv7. Other not armv7
i.MX can profit of the same shared code. Move these files
into a directory accessible for all, similar to plat-mxc
in linux.

Signed-off-by: Stefano Babic <sbabic@denx.de>

The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces
support for the i.MX6Q MMC host controller USDHC.

MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock
of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC
IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times
higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()).

Signed-off-by: Michael Langer <michael.langer@de.bosch.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Jason Liu <r64343@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
  added but just fix the checkpatch errors in the old file and remove
  the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

It can be optimised out by the compiler otherwise resulting
in obscure errors like a board not booting.

This has been documented in README since 2006 when these were
first fixed up for GCC 4.x.

Signed-off-by: John Rigby <john.rigby@linaro.org>

Fix some additional places.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-By: Albert ARIBAUD <albert.aribaud@free.fr>

Rename mx51 to mx5 in order to support more mx51
like-style SOCs such as MX53 and the followings.

Signed-off-by: Jason Liu <r64343@freescale.com>

The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9

Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.

The two architectures are similar enough that substantial code can be shared.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

The patch removes warnings at compile time and provides
some cleanup code:
- Removed comment on NAND (not yet supported) from lowlevel_init.S
- Removed NFMS bit definition from imx-regs.h
  The bit is only related to MX.25/35 and can lead to confusion
- Moved is_soc_rev() to soc specific code (removed from mx51evk.c)

Signed-off-by: Stefano Babic <sbabic@denx.de>

The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.

Signed-off-by: Stefano Babic <sbabic@denx.de>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>

Signed-off-by: Stefan Roese <sr@denx.de>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

interrupt_init() and dtimer_intr_setup() are placed in interrupts.c. Added interrupts.o to Makefile

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>

- update ARM boards to use constants from mach-types.h