The bmode command forces the SoC to use a specific boot device
by writing its boot mode into SRC_GPR9, and notifying the SoC of
the change using SRC_GPR10[28] bit: if the bit is on, bootROM
uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine
the boot device.

SPL on the other hand is oblivious to this distinction, so once
the bootROM loads SPL from the device configured in SRC_GPR10,
SPL will attempt to load U-Boot from the device configured in
SRC_SMBR1, which is not updated by the bootROM to the value in
SRC_GPR9.

The result is that the selected boot device is not used across all
the boot stages.

Update spl_boot_device() to look at gpr9 when necessary.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Heiko Schocher <hs@denx.de>

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This reverts commit 1e96220a.

Remove duplicated vxworks.h header.
The same change was done by
"ARM: prevent compiler warnings from bootm.c"
(sha1: 8d196e52)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and
it is defined in ./.config but not in spl/.config,
so pin_init() should be called from the normal image
so that UART works correctly.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

This commit merges
  arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c
to
  arch/arm/cpu/armv7/uniphier/board_postclk_init.c

Because PH1-Pro4 does not have the BCU block, add __weak to
bcu_init().

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

The function sg_set_pinsel is useful for switching I/O pins
but it can be only used in C code.  This commit adds a simple
macro that is available in asm code.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Support EHCI host driver used on Panasonic UniPhier platform.
Since Device Tree is not supported on UniPhier yet, the base address
of USB cores are passed from board files (platdevice.c).

TODO for me:
Move the base address to device trees.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>

This commit adds register defines of MIO (Media I/O) block
of UniPhier platform.  This file is necessary to control
the reset signals of the USB cores.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

These IO pins are necessary for port power control and
over current detect.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

If a support card is attached to the main board, the on-board
SMSC9118 LAN controller is available.  It must be kept in reset
state for a while on start-up.

When the board is kicked via a debbuger rather than pushing the
hardware reset button, on-board chips are not reset; in this case
the reset signals should be asserted by software.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

cppcheck reports:

[arch/arm/cpu/arm926ejs/mxs/timer.c:96]: (error) Uninitialized
variable: now

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

There are a number of places where U-Boot intentionally and legally
accesses physical address 0x0000, for example when installing
exception vectors on systems where these are located in low memory.

Add "cppcheck-suppress nullPointer" comments to silence cppcheck
where this is intentional and legal.

Signed-off-by: Wolfgang Denk <wd@denx.de>

CompuLab cm-t3517 is Computer on Module (CoM) based on AM3517 SoC.
Features: up to 256MB DDR2, up to 512MB NAND, USB hub, mUSB, WiFi, BT,
Analog audio codec, touch screen controller, LED.

Add basic support including:
LED, Serial console, NAND, MMC, GPIO, I2C, 256MB DRAM.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>

Current get_board_rev() function returns a hard coded value which is
obviously incorrect for the majority of boards.
Allow boards to provide a correct implementation by making this
function weak.
In addition open code the trivial and useless BOARD_REV_ID define and
adjust the comment.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@ti.com>

The Keystone2 Lamar SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2L SoCs.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

Keystone2 Lamar SoC uses the same keystone SerDes driver.
All Keystone2 EVM boards currently use SerDes driver, so move
CONFIG_TI_KEYSTONE_SERDES to common configuration file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

The Keystone2 Lamar SoC uses the same keystone navigator.
Move queue numbers to common hardware file, as all Keystone2 SoCs
have the same ones.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>

Add a driver for the designware serial UART used on sunxi. This just
redirects to the normal ns16550 driver.

Add a stdout-path to the device tree so that the correct UART is chosen.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

With driver model we will have access to a bank pointer, so we want to
use it rather than converting back to a number, and then back to a
bank pointer. Add functions to provide this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

For now we won't want to mess with the existing configurations. Create a
new one which will enable device tree and driver model. Note that this
brings the device tree binary into u-boot-sunxi-with-spl.bin.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

These are from Linux 3.17-rc7 (commit fe82dcec). U-Boot only uses a small
portion of these, but we may as well have something to look forward to.

The total compiled size is about 25KB.

Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Mostly automatic with:
    sed -i -e 's/CONFIG_\(SUN[45678]I\)/CONFIG_MACH_\1/g' $(git grep -l CONFIG_SUN[45678]I)
followed by removing the relevant #defines from include/configs/sun?i.h by
hand.

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

And make TARGET_SUN[45678]I a choice variable under this.

configs updated with:
    sed -i -e 's/^\(\+S:\)\?CONFIG_TARGET_SUN.I=y/\1CONFIG_ARCH_SUNXI=y\n&/g' configs/*

Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>

If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x70000000.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0xB0000000.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Initialization of L2CTLR[5] was set only as R8A7790 by commit
237faf09.
However, initialization of cash needs to be performed continuously.
This changes into the processing which continues initialization of
L2CTLR[5] into L2CTLR cash and performs it.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

On mx6 sabreauto board, there are two USB ports:
0: OTG
1: HOST
The EHCI driver is enabled for this board, but the IOMUX and VBUS power
control is not implemented, which cause both USB port failed to work.
This patch fix the problem by adding the board support codes.

Since the power control uses the GPIO pin from port expander MAX7310,
the PCA953X driver is enabled for accessing the MAX7310.

The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting
its daisy chain. Add a new function "imx_iomux_set_gpr_register" to
handle GPR register setting.

Signed-off-by: Ye.Li <B37916@freescale.com>

Set the USDHC1-3 IOMUX settings which are used for mx6slevk board.

Signed-off-by: Ye.Li <B37916@freescale.com>

For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.

Signed-off-by: Ye.Li <B37916@freescale.com>

For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix
the get_ipg_per_clk function to support it.

Signed-off-by: Ye.Li <B37916@freescale.com>

The MX6SL has the perclk_clk_sel to select the perclk source. Add
its define in CCM

Signed-off-by: Ye.Li <B37916@freescale.com>

Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set,
the GPT will select a high frequency clock as clock source.
Otherwise, the GPT will stay to use 32Khz OSC as clock source.

In the implementation, since only the GPT on i.MX6 series provide the
clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6
compile the driver), if the configuration is set, the perclk will be
selected as clock source.
MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they
don't have the 24Mhz OSC clock source option, so also select the perclk
for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so
eventually the clock comes from OSC 24Mhz.

Signed-off-by: Ye.Li <B37916@freescale.com>

Commit d58a9451 (ppc/arm: zap EMK boards) removed
TOP* boards support but missed to remove entries in Kconfig.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>

[1] arch/arm/include/asm/arch-at91/at91_shdwn.h
 The top9000 was the last board to use this header file.
 It was removed by commit d58a9451 (ppc/arm: zap EMK boards).

[2] board/matrix_vision/common/*
 Some Matrix Vision boards were dropped by commit e7a56563
 (powerpc: mpc83xx: remove board support for MERGERBOX and MVBLM7)
 and commit af55e35d
 (powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR).
 Since then these files have been unused.

[3] include/usb/omap1510_udc.h
  The omap5912osk was the last board to use this header file.
  It was removed by commit 62d636aa
  (omap: remove omap5912osk board support).

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-By: Wolfgang Denk <wd@denx.de>

fix typos in video pll related register names and bit defines

Signed-off-by: Soeren Moch <smoch@web.de>

This patch adds extra gpio part addresses to exynos4
and exynos4x12_gpio_data arrays, which are required
since the gpio enum lists are linear

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

After remove the offsets in Exynos4/4x12 gpio enums,
an additional gpio base addresses are required.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>