Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.

Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>

Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.

Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>

The dfu_alt_info_spl variable allows passing a starting point
for the binary to be flashed in the SPI NOR.

For example, if we have 'dfu_alt_info_spl=spl raw 0x400', this means
that we want to flash the binary starting at address 0x400.

In order to do so we need to erase the entire sector and write to
the the subsequent SPI NOR sectors taking such start address
into account for the address calculations.

Tested by succesfully writing SPL binary into 0x400 offset and
the u-boot.img at offset 64 kiB of a SPL NOR.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Use lldiv for the math]
Signed-off-by: Tom Rini <trini@konsulko.com>

SPI NOR flashes need to erase the entire sector size and we cannot pass
any arbitrary length for the erase operation.

To illustrate the problem:

Copying data from PC to DFU device
Download    [=========================] 100%       478208 bytes
Download done.
state(7) = dfuMANIFEST, status(0) = No error condition is present
state(10) = dfuERROR, status(14) = Something went wrong, but the
device does not know what it was
Done!

In this case, the binary has 478208 bytes and the M25P32 SPI NOR
has an erase sector of 64kB.

478208  = 7 entire sectors of 64kiB + 19456 bytes.

Erasing the first seven 64 kB sectors works fine, but when trying
to erase the remainding 19456 causes problem and the board hangs.

Fix the issue by always erasing with the erase sector size.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>

- Add deletions from August 30 2015.
- A few from Sept 12, one from Oct 2nd.

Signed-off-by: Tom Rini <trini@konsulko.com>

Upon further review when populating README.scrapyard, inetspace_v2_cmc
is a variant on netspace_v2 and not just an orphan config.

This reverts commit 653600a7.

Signed-off-by: Tom Rini <trini@konsulko.com>

Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config.  To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.

This reverts commit 1363740e.

Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>

Add in the commit IDs / dates for boards removed on Sept 2nd.

Signed-off-by: Tom Rini <trini@konsulko.com>

Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>

The default dockstar configuration for U-Boot currently causes it to
overrun the environment area, so that a "saveenv" command bricks the
device.  This patch moves the environment to a higher address to avoid
that.

Signed-off-by: Eric Cooper <ecc@cmu.edu>

On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"

Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

There are various toolchain issues that cause us to produce invalid
binaries with certain gcc 4.8.x and 4.9.x versions when we don't pass
this flag in.

Tested-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Signed-off-by: Tom Rini <trini@konsulko.com>

We need "u-boot,dm-pre-reloc" in the socfpga_cyclone5_socdk.dts file in
order for the SPL to use SD/MMC.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Update the L2 AUX CTRL settings for the SoCFPGA.

Enabling D and I prefetch bits helps improve SDRAM performance on the
platform.

Also, we need to enable bit 22 of the L2. By not having bit 22 set in the
PL310 Auxiliary Control register (shared attribute override enable) has the
side effect of transforming Normal Shared Non-cacheable reads into Cacheable
no-allocate reads.

Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cec
(vf610: refactor DDRMC code).

Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>

Add 'volatile' qualifier to the asm statement in get_cr()
so that the statement is not optimized out by the compiler.

(http://comments.gmane.org/gmane.linux.linaro.toolchain/5163

)

Without the 'volatile', get_cr() returns a wrong value which
prevents enabling the MMU  and later causes a PCIE VA access
failure.

Signed-off-by: Alison Wang <alison.wang@freescale.com>

PCI driver currently hangs on mx6qp.

Toggle the reset bit with the appropriate timings to fix the issue.

Based on the FSL kernel driver implementation.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>

Initialize all GICD_IGROUPRn registers and set up GICC_CTLR to enable
interrupts to the primary CPU. This fixes issues seen after booting a
Linux kernel from U-Boot.

Suggested-by: Marc Zyngier <marc.zyngier@arm.com>
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.

For EL1, only bit 23 is not reserved, so only write bit 31 as 1.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Currently, the device tree relocation is disabled, likely to
keep some DDR3 RAM at the end for Cortex-M4 firmwares. This
can be archived using bootm_size, which limits the image
processing range of the boot commands.

Move the device tree standard load address to a higher address
which aligns better with what we are doing on other boards.

Signed-off-by: Stefan Agner <stefan@agner.ch>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>

Commit 3f353cec ("vf610: refactor DDRMC code") changed the original
bstlen field from 3 to 0.

Restore the original value for proper behaviour.

Based on the patch from Anthony Felice <tony.felice@timesys.com>
for the vf610twr board.

Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

This resyncs the driver changes with the Linux version of the
driver. The driver received some feedback in the LKML and got
recently acceppted, the latest version can be found here:
https://lkml.org/lkml/2015/9/2/678



Notable changes are:
- On ECC error, reread OOB and count bit flips in OOB too.
  If flipped bits are below threshold, also return an empty
  OOB buffer.
- Return the amount of bit flips in vf610_nfc_read_page.
- Use endianness aware vf610_nfc_read to read ECC status.
- Do not enable IDLE IRQ (since we do not operate with an
  interrupt service routine).
- Use type safe struct for buffer variants (vf610_nfc_alt_buf).
- Renamed variables in struct vf610_nfc (column and page_sz)
  to reflect better what they really representing.

The U-Boot version currently does not support RAW NAND write
when using the HW ECC engine.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tested-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Tested-by: Stefan Agner <stefan@agner.ch>
Acked-by: Scott Wood <scottwood@freescale.com>

Add more debug printfs in do_sdhci_init() for calls
that can potentially fail.

Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

In case sdhci_get_config() or do_sdhci_init() fail, show
the error code that was returned.

Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

exynos_mmc_init() always returns zero, so for the caller
it looks like it never fails.

Correct this by returning the error code of process_nodes().
For process_nodes() do something similar and return early
when do_sdhci_init() fails.

v2: Only fail in process_nodes() if we fail on all
    available nodes.

Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

This makes sure that setting the host_caps in s5p_sdhci_core_init()
doesn't operate on potentially uninitialized memory.

Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Add boot script (boot.scr) support. If no boot script are
found, it boots as usual.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Replace 'fatload' command by 'load', to be able to use EXT*
partitions while keeping FAT partition compatibility.

Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Since commit 623d96e8("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.

Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.

This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e8("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.

In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.

This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.

Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Create fsl_wdog.h to store the watchdog registers and bit fields.

This can be useful when accesses to the watchdog block are made from other
parts, such as arch/arm/ cpu code.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: Tom Rini <trini@konsulko.com>