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  1. Jul 10, 2018
  3. Jul 05, 2018
  5. Jul 02, 2018
  7. Jun 29, 2018
    • Jagan Teki's avatar
      usb: sunxi: Use proper reg_mask for clock gate, reset · 9c22aec4
      Jagan Teki authored 
      
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: default avatarJagan Teki <jagan@amarulasolutions.com>
      9c22aec4
    • Zeng Tao's avatar
      usb: ohci: change the NUM_EDs from 8 to 32 · 11080bf6
      Zeng Tao authored 
      
For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.

Signed-off-by: default avatarZeng Tao <prime.zeng@hisilicon.com>
      11080bf6
    • Vasily Khoruzhick's avatar
      usb: sunxi: ohci: make ohci_t the first member in private data · ebbc23a0
      Vasily Khoruzhick authored 
      
ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.

Fixes 831cc98b ("usb: sunxi: Simplify ccm reg base code")

Signed-off-by: default avatarVasily Khoruzhick <anarsoul@gmail.com>
      ebbc23a0
  9. Jun 28, 2018
    • Marek Vasut's avatar
      sf: Enable FSR polling on N25Q256(A) · 069b746a
      Marek Vasut authored 
      
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
      069b746a
    • Hannes Schmelzer's avatar
      spi: omap3: fix claim/release bus within DM · c0eaffa0
      Hannes Schmelzer authored 
      
The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.

Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.

We change now the things as following for having a working SPI instance
in DM:

- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.

- in release bus we just reset the modulctrl to the reset-value (spi-
slave)

Signed-off-by: default avatarHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: default avatarJagan Teki <jagan@openedev.com>
      c0eaffa0
    • Andrew Thomas's avatar
      dwc2 USB controller hangs with lan78xx · af15946a
      Andrew Thomas authored 
      
This bug is the combination of dwc2 USB controller and lan78xx
USB ethernet controller, which is the combination in use on
the Raspberry Pi Model 3 B+.

When the host attempts to receive a packet, but a packet has not
arrived, the lan78xx controller responds by setting BIR
(Bulk-In Empty Response) to NAK. Unfortunately, this hangs
the USB controller and requires the USB controller to
be reset.

The fix proposed is to have the lan78xx controller respond
by setting BIR to ZLP.

Signed-off-by: default avatarAndrew Thomas <andrew.thomas@oracle.com>
Tested-by: default avatarPeter Robinson <pbrobinson@gmail.com>
Reviewed-by: default avatarAlexander Graf <agraf@suse.de>
      af15946a
  11. Jun 27, 2018