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  1. Mar 21, 2017
  2. Mar 20, 2017
  3. Mar 19, 2017
  4. Mar 17, 2017
  5. Mar 15, 2017
  6. Mar 10, 2017
  7. Feb 17, 2017
  8. Jan 28, 2017
    • Marcin Niestroj's avatar
      board/chiliboard: Add support for chiliBoard · ab38bf6a
      Marcin Niestroj authored
      
      chiliBoard is a development board which uses chiliSOM as its base.
      
      Hardware specification:
       * chiliSOM (TI AM335x, DRAM, NAND)
       * Ethernet PHY (id 0)
       * USB host (usb1)
       * MicroSD slot (mmc0)
      
      Signed-off-by: default avatarMarcin Niestroj <m.niestroj@grinn-global.com>
      Reviewed-by: default avatarTom Rini <trini@konsulko.com>
      ab38bf6a
    • maxims@google.com's avatar
      aspeed: Add drivers common to all Aspeed SoCs · 4697abea
      maxims@google.com authored
      
      Add support for Watchdog Timer, which is compatible with AST2400 and
      AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
      does not follow the driver model. It also uses fixed clock, so no clock
      driver is needed.
      
      Add support for timer for Aspeed ast2400/ast2500 devices.
      The driver actually controls several devices, but because all devices
      share the same Control Register, it is somewhat difficult to completely
      decouple them. Since only one timer is needed at the moment, this should
      be OK. The timer uses fixed clock, so does not rely on a clock driver.
      
      Add sysreset driver, which uses watchdog timer to do resets and particular
      watchdog device to use is hardcoded (0)
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      4697abea
  9. Jan 27, 2017
  10. Jan 25, 2017
  11. Jan 24, 2017
  12. Jan 22, 2017
    • Masahiro Yamada's avatar
      ARM: uniphier: make SPL optional for ARVv8 SoCs · 561ca649
      Masahiro Yamada authored
      
      We may want to run different firmware before running U-Boot.  For
      example, ARM Trusted Firmware runs before U-Boot, making U-Boot
      a non-secure world boot loader.  In this case, the SoC might be
      initialized there, which enables us to skip SPL entirely.
      
      This commit removes "select SPL" to make it configurable.  This
      also enables the Multi SoC support for the UniPhier ARMv8 SoCs.
      (CONFIG_ARCH_UNIPHIER_V8_MULTI)  Thanks to the driver model and
      Device Tree, the U-Boot proper part is now written in a generic way.
      The board/SoC parameters reside in DT.  The Multi SoC support
      increases the memory footprint a bit, but the U-Boot proper does
      not have strict memory constraint.  This will mitigate the per-SoC
      (sometimes per-board) defconfig burden.
      
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      561ca649
  13. Jan 20, 2017
    • Tom Rini's avatar
      ARM: Default to using optimized memset and memcpy routines · 40d5534c
      Tom Rini authored
      
      We have long had available optimized versions of the memset and memcpy
      functions that are borrowed from the Linux kernel.  We should use these
      in normal conditions as the speed wins in many workflows outweigh the
      relatively minor size increase.  However, we have a number of places
      where we're simply too close to size limits in SPL and must be able to
      make the size vs performance trade-off in those cases.
      
      Cc: Philippe Reynes <tremyfr@yahoo.fr>
      Cc: Eric Jarrige <eric.jarrige@armadeus.org>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Magnus Lilja <lilja.magnus@gmail.com>
      Cc: Lokesh Vutla <lokeshvutla@ti.com>
      Cc: Chander Kashyap <k.chander@samsung.com>
      Cc: Akshay Saraswat <akshay.s@samsung.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Stefan Roese <sr@denx.de>
      Signed-off-by: default avatarTom Rini <trini@konsulko.com>
      Acked-by: default avatarStefan Roese <sr@denx.de>
      Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
      40d5534c
  14. Jan 18, 2017
  15. Jan 05, 2017
  16. Dec 27, 2016
    • Masahiro Yamada's avatar
      ARM: revive CONFIG_USE_ARCH_MEMCPY/MEMSET for UniPhier and Tegra · 085be482
      Masahiro Yamada authored
      
      Commit be72591b ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to
      Kconfig") is misconversion.
      
      The original logic in include/configs/uniphier.h was as follows:
      
        #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64)
        #define CONFIG_USE_ARCH_MEMSET
        #define CONFIG_USE_ARCH_MEMCPY
        #endif
      
      This means those configs were enabled when building U-Boot proper,
      but disabled when building SPL.  Likewise for Tegra.
      
      Now "depends on !SPL" prevents any boards with SPL support
      from reaching these options.  This changed the behavior for
      UniPhier and Tegra SoC family.
      
      Please notice these two options only control the U-Boot proper
      build.  As you see arch/arm/Makefile, ARM-specific memset/memcpy
      are never compiled for SPL.  So, __HAVE_ARCH_MEMCPY/MEMSET should
      not set for SPL.
      
      Fixes: be72591b ("Kconfig: Move USE_ARCH_MEMCPY/MEMSET to Kconfig")
      Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      Reviewed-by: default avatarFabio Estevam <fabio.estevam@nxp.com>
      085be482
  17. Dec 16, 2016
  18. Dec 11, 2016
  19. Dec 06, 2016
    • Marek Vasut's avatar
      ARM: socfpga: Add boot0 hook to prevent SPL corruption · beee6a30
      Marek Vasut authored
      
      Valid Altera SoCFPGA preloader image must contain special data at
      offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or
      0x50. These addresses are by default used by U-Boot's vector table
      and a piece of reset handler, thus a valid preloader corrupts those
      addresses slightly. While this works most of the time, this can and
      does prevent the board from rebooting sometimes and triggering this
      issue may even depend on compiler.
      
      The problem is that when SoCFPGA performs warm reset, it checks the
      addresses 0x40..0x4b in SRAM for a valid preloader signature and
      header checksum. If those are found, it jumps to address 0x4c or
      0x50 (this is unclear). These addresses are populated by the first
      few instructions of arch/arm/cpu/armv7/start.S:
      
      ffff0040 <data_abort>:
      ffff0040:       ebfffffe        bl      ffff0040 <data_abort>
      
      ffff0044 <reset>:
      ffff0044:       ea000012        b       ffff0094 <save_boot_params>
      
      ffff0048 <save_boot_params_ret>:
      ffff0048:       e10f0000        mrs     r0, CPSR
      ffff004c:       e200101f        and     r1, r0, #31
      ffff0050:       e331001a        teq     r1, #26
      
      Without this patch, the CPU will enter the code at 0xffff004c or
      0xffff0050 , at which point the value of r0 and r1 registers is
      undefined. Moreover, jumping directly to the preloader entry point
      at address 0xffff0000 will also fail, because address 0xffff004.
      is invalid and contains the preloader magic.
      
      Add BOOT0 hook which reserves the area at offset 0x40..0x5f and
      populates offset 0x50 with jump to the entry point. This way, the
      preloader signature is stored in reserved space and can not corrupt
      the SPL code.
      
      Signed-off-by: default avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Stefan Roese <sr@denx.de>
      Tested-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
      beee6a30
  20. Dec 05, 2016
  21. Dec 04, 2016
  22. Nov 29, 2016
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