- Feb 21, 2014
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David Feng authored
This patch deal with error message of mtest command. When test failed, the mtest command will output error information that include memory address and value. But the address field is not correct or misleading. Signed-off-by:
David Feng <fenghua@phytium.com.cn>
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York Sun authored
This function has been around for powerpc. It is used for systems with memory more than CONFIG_MAX_MEM_MAPPED. In case of non-contiguous memory, this feature can limit U-boot to one block without going over the limit. Signed-off-by:
York Sun <yorksun@freescale.com> Acked-by:
Albert ARIBAUD <albert.u.boot@aribaud.net>
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York Sun authored
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by:
York Sun <yorksun@freescale.com>
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York Sun authored
DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by:
York Sun <yorksun@freescale.com>
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York Sun authored
Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by:
York Sun <yorksun@freescale.com>
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Christian Eggers authored
do_bootm_standanlone() calls ntohl(images->ep) which is wrong because endianess conversion has already been done: do_bootm() \-do_bootm_states() +-bootm_find_os() | \-images.ep = image_get_ep(); | \-uimage_to_cpu(hdr->ih_ep); \-boot_selected_os() \-do_bootm_standanlone() Without this conversion the code works correctly at least on AT91SAM9G45. On big endian systems there should be no difference after applying this patch because uimage_to_cpu(x) and ntohl(x) both expand to 'x'. Signed-off-by:
Christian Eggers <ceggers@gmx.de>
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Axel Lin authored
Use default_serial_puts() instead of duplicating the implementation. Signed-off-by:
Axel Lin <axel.lin@ingics.com>
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Tom Rini authored
We have an unused FAT implementation in fs/fdos, remove. Signed-off-by:
Tom Rini <trini@ti.com>
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git://git.denx.de/u-boot-spiTom Rini authored
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Alexey Brodkin authored
In case of little-endian ARC700 instructions (which may include target address) are encoded as middle-endian. That's why it's required to swap bytes after read and ten right before write back. But in case of big-endian ARC700 instructions are encoded as a plain big-endian. Thus no need for byte swapping. Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com> Cc: Francois Bedard <fbedard@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Noam Camus <noamc@ezchip.com>
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Alexey Brodkin authored
Proper spelling of the boad marketing name is with upper case. So changing it from lower case to upper case here. Cc: Tom Rini <trini@ti.com> Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com>
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Alexey Brodkin authored
With accepted change to DW GMAC driver - 92a190aa (net/designware - switch driver to phylib usage) we need to update this board because "designware_initialize" now accepts only 2 parameters instead of 4. Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com>
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Alexey Brodkin authored
This is required for proper functionality on big-endian targets. Memory-mapped registres of ARC UART are not 32-bit words but 8-bit bytes so on little-endian target either acessor (_l or _b) works fine. On big-endian only _b accessors works as expected. Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Tom Rini <trini@ti.com>
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Alexey Brodkin authored
Explanation is in in-lined comment. Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Noam Camus <noamc@ezchip.com> Cc: Tom Rini <trini@ti.com>
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- Feb 20, 2014
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git://git.denx.de/u-boot-armTom Rini authored
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Tom Rini authored
With d6a320d5 we moved some clock externs out of blackfin_local.h and into clock.h but now need to include <asm/clock.h> in more drivers to avoid warnings. Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
Tom Rini <trini@ti.com>
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Łukasz Majewski authored
The commit: "EXT4: Fix number base handling of "ext4write" command" SHA1: f7740f77 Cleaned up the ext4write command format. This commit shall be regarded as a follow up, since the DFU subsystem is using those commands for its normal operation. Signed-off-by:
Lukasz Majewski <l.majewski@samsung.com>
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Masahiro Yamada authored
Commit 5ab502cb gathered all device tree sources to arch/$(ARCH)/dts/. So tegra124-venice2.dts also must go to arch/arm/dts directory to build venice2 board. (Commit 5ab502cb had been posted before venice2 board support was merged. So an unvisible conflict happened.) Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com>
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Albert ARIBAUD authored
Conflicts: Makefile drivers/net/npe/Makefile These two conflicts arise from commit 0b2d3f20 ("ARM: NET: Remove the IXP NPE ethernet driver") and are resolved by deleting the drivers/net/npe/Makefile file and removing the CONFIG_IXP4XX_NPE line from Makefile.
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Alexey Brodkin authored
This file was only required for compilation of designware_i2c driver. Since explicit inclusion of "hardware.h" is now removed from the driver we may safely remove this empty header as well. Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Armando Visconti <armando.visconti@st.com>
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Alexey Brodkin authored
As soon as all boards have their CONFIG_SYS_I2C_BASE defined in configuration files instead of "asm/arch/hardware.h" it's safe to remove the inclusion in question and make driver platform-independent. Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Armando Visconti <armando.visconti@st.com> Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com>
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Alexey Brodkin authored
Having CONFIG_SYS_I2C_BASE requires DW I2C driver to explicitly include <arch/hardware.h> which other platforms may not have at all. It's always good to have a driver platform-independent. Signed-off-by:
Alexey Brodkin <abrodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vipin Kumar <vipin.kumar@st.com> Cc: Armando Visconti <armando.visconti@st.com>
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Hannes Petermaier authored
Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by:
Hannes Petermaier <oe5hpm@oevsv.at> Cc: Heiko Schocher <hs@denx.de>
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Marek Vasut authored
Make sure the I2C write queue is empty before leaving the mxs_i2c_write(). If we start and I2C write and only wait for ACK, the MXS I2C IP block may enter next operation while still processing the write aftermath internally. This will in turn disrupt one or more subsequent transfer(s). A testcase for this issue is as such. This testcase is also interesting because the first I2C_WRITE which becomes disruptive happens in the 'i2c read' command. The 'i2c read' command first uses I2C_WRITE to send I2C address of the chip and then uses I2C_READ to read data from the chip. After this command completes, the 'i2c probe' will use sequence of I2C_WRITE commands to probe the I2C bus. The problem is that the first I2C_WRITE disrupted the I2C IP block operation and this sideeffect propagates all the way to this next I2C_WRITE used by the 'i2c probe' call. The result is the 'i2c probe' receives an ACK on I2C address 0x00, even if this ACK was owned by the previous I2C_WRITE operation. Note that the 'i2c read' command must read from a valid I2C chip address. Wrong: > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 00 50 51 With this patch > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 50 51 Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
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Chin Liang See authored
Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by:
Chin Liang See <clsee@altera.com> Acked-by:
Alexey Brodkin <Alexey.Brodkin@synopsys.com> Cc: Tom Rini <trini@ti.com> cc: Armando Visconti <armando.visconti@st.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
add support for bootcounter on an i2c device. And add a README for all bootcounter options. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Scott Jiang authored
The ADI twi peripheral is not binding to Blackfin processor only. Access i2c registers by standard io functions. Fix coding style. Signed-off-by:
Scott Jiang <scott.jiang.linux@gmail.com> Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com>
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Sonic Zhang authored
The ADI twi peripheral is not binding to Blackfin processor only. Change to a generic name. Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com>
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Sonic Zhang authored
Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com>
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Sonic Zhang authored
Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com>
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Michael Burr authored
Initialize the second i2c controller. Signed-off-by:
Michael Burr <michael.burr@logicpd.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Michael Burr authored
Fixed bug with alen == 0 in 'i2c_write', 'i2c_read' Further minor corrections: - Write 'address' register before 'data' register. - Write 'transfer_size' register before 'address' register. Signed-off-by:
Michael Burr <michael.burr@logicpd.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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- Feb 19, 2014
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Tom Rini authored
Signed-off-by:
Tom Rini <trini@ti.com>
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Masahiro Yamada authored
In Kbuild, every makefile must have non-empty obj- or obj-y. Otherwise, built-in.o will not be created and the link stage will fail. Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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Masahiro Yamada authored
There is a strange comment in fit_image_load(). This function can be used for loading Kernel Image, FDT as well as ramdisk. Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Acked-by:
Simon Glass <sjg@chromium.org>
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Masahiro Yamada authored
If the whole code is surrounded by #ifdef(CONFIG_ ) .. #endif, it should be moved to Makefile. Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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Masahiro Yamada authored
- When CONFIG_DISPLAY_CPUINFO is not enabled, print_cpuinfo() should be defined as an empty function in a header, include/common.h - Remove #ifdef CONFIG_DISPLAY_CPUINFO .. #endif from caller, common/board_f.c and arch/arm/lib/board.c - Remove redundant prototypes in arch/arm/lib/board.c, arch/arm/include/asm/arch-am33x/sys_proto.h and board/nokia/rx51/rx51.h, keeping the one in include/common.h - Add #ifdef CONFIG_DISPLAY_CPUINFO to the func definition where it is missing Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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Masahiro Yamada authored
Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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Masahiro Yamada authored
CONFIG_SYS_GBL_DATA_SIZE is not used any more. The size of struct "global_data" is automatically calculated by asm-offsets. (See lib/asm-offsets.c) GENERATED_GBL_DATA_SIZE should be used instead of CONFIG_SYS_GBL_DATA_SIZE. Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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Masahiro Yamada authored
It is convenient to have all device trees on the same SoC compiled. It allows for later easy repackaging without the need to re-run the make file. - Build device trees with the same SoC under arch/$(ARCH)/dts - Copy the one specified by CONFIG_DEFAULT_DEVICE_TREE or DEVICE_TREE=... to dts/dt.dtb Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com>
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