Add a build target to generate 'boot.bin' which includes SPL. This is
used by the platforms BootROM to load SPL directly.

This change also conditionally changes what the 'boot.bin' target
generates depending on the SoC. Leaving the behaviour unchanged for the
AT91 targets.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>

As with other platforms vendors love to create their own boot header
formats. Xilinx is no different and for the Zynq platform/SoC there
exists the "boot.bin" which is read by the platforms bootrom. This
format is described to a useful extent within the Xilinx Zynq TRM.

This implementation adds support for the 'zynqimage' to mkimage. The
implementation only considers the most common boot header which is
un-encrypted and packed directly after the boot header itself (no
XIP, etc.). However this implementation does take into consideration the
other fields of the header for image dumping use cases (vector table and
register initialization).

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Enable TI phy for Xilinx ZynqMP platform.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Code is taken from Linux kernel driver (v4.2).

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

OF_CONTROL is enabled by default for all Zynq boards.
The difference between two boot images is done by OF_SEPARATE
or OF_EMBED macros.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Put jump trampoline to TCM at 0 and setup R5 reset address to 0.
Jump trampoline ensures that jump to the right location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

The commit mentioned below replaced return statements inside a switch so
that other code could be called after the switch. However, it didn't add
any break statements, causing the cases to run together. Fix this.

Reported-by: Coverity (CID 132282, 132283)
Fixes: 7861204c ("itest: make memory access work under sandbox")
Signed-off-by: Stephen Warren <swarren@nvidia.com>

Check the result code of all command that are executed. Without this,
if the fallocate invocation fails (this feature is not supported on ext3
filesystems for example) then a zero-length output file will be created,
and subsequent the mkfs and mount invocations will fail, which will cause
the subsequent dd invocation to attempt to fill up the host's entire free
disk space. That's not a nice user experience!

Related, if fallocate does fail, try to create the test disk image using
dd instead. That should work everywhere.

Fixes: 4a282742 ("test: fat: add test of non-contiguous file reads")
Signed-off-by: Stephen Warren <swarren@nvidia.com>

gcc 4.4.3 (which is the default native compiler on x86-64 Ubuntu 10.04)
doesn't seem to like initializers for sub-fields of anonymous unions.
Solve this by replacing the initialization with an assignment. This
fixes:

lib/lz4_wrapper.c: In function ‘ulz4fn’:
lib/lz4_wrapper.c:97: error: unknown field ‘raw’ specified in initializer

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

This board uses the same CPU (8309) as VECT1. The memory however is
different since it has NAND Flash, the NOR Flash partitioning is
different and of course the FPGAs as well.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Christoph Dietrich <christoph.dietrich@keymile.com>

It should be after the u-boot reserved sectors and before the env
sectors, since the solution used for kmvect1 (tell the linker to put the
firmware into the u-boot produced binary, at the end of the area) should
be the exception.

The #define is only "conditional" so that we can still support kmvect1.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

The hardcoded value are bad, since the address could change between
different boards.

Furthermore, the relevant #defines are set only if #undefined here, so
that they can be changed by some boards if required.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

Setting dip_switch 3 and 4 also will run bootloader in COGE3 and COGE6
It is required remove local mgmt IP address, when DIP Switch PIN3 is
enabled. DIP Switch 4 also enabled to avoid u-boot update in future
for DIP switch enhancements.

Signed-off-by: Bagavathiannan Palanisamy <Bagavathiannan.Palanisamy@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

The ODT parameters for km8360 set the ODT_WR_ACS bit in u-boot KM-2011.09
that is used in the release bootpackage for kmcoge5ne. During the
transition from the kmeter1 to km8360 this was changed to
ODT_RD_ONLY_CURRENT, which is uncorrect and causes faulty RAM accesses at
low temperatures.

This is now changed to ODT_WR_ONLY_CURRENT which is the equivalent of
ODT_WR_ACS.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

For consistency with all the other km83xx plaforms, this should also be
defined for km8309. The same settings as for km8321 are taken.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

On the km8321 boards is CONFIG_SYS_DDRCDR not defined, which leads to
the DDRCDR not being configured at startup and still containing the
reset value.

The required settings for our km8321 hardware designs are different than
the reset value and must be set with CONFIG_SYS_DDRCDR, that is used
by mpc83xx's cpu_init_f function at early CPU initialization.

The important settings are the DDR2 internal voltage level and the
half-strength "drivers".

In our case where the DRAM chips are soldered on board and the routing
for these signals under control, half-strength is sufficient as a few
measurements done in the lasts have shown. Since all the hardware
qualification tests have been performed with half strength, the nominal
strength settings are removed in favor of the default reset half
strength settings.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

commit 0a4f88b9 removed the usage of our setports function, but the
function itself were not removed. So toss it it's dead code.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

We use CONFIG_OF_LIBFDT and CONFIG_OF_BOARD_SETUP on all our powerpc
targets, so there is no need to check these defines within our C code.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

We use the same settings for open firmware defines on all our powerpc
targets, so move them from the CPU specific headers to the common
powerpc header.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

128kByte and 3,986MB may be in the future too little for kernel the fdt
blob respectively the kernel image. So increase the reserved areas here,
we have the space for this.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

On mgcoge3ne we also want to start the test application if the testpin
is asserted. But we don't have a full POST test support yet. So simply
add a function to read the testpin value.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

The get_pin and set_pin funciton was only used for pins on Port D and
therefore the value was hard coded in the function. Enhance this with a
parameter, that we are able to use this functions for other ports too.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

This board is similar to TUXX1, but it has differend FPGAs.

Signed-off-by: Christoph Dietrich <christoph.dietrich@keymile.com>
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

Search for the kernel and DTBs in a folder named PRODUCTNAME (found in the IVM)
at the TFTP server instead of the u-boot boardname.

Signed-off-by: Tobias Müller <Tobias.Mueller@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

When loading the dtb file via tftp we should load the one which matches
boardId and hwKey and not a common one for the boardname. We have boards
were different hwKeys are used and then we may load an incorrect dtb
file. If no fdt_bid_kwkey.dtb file is not a fallback to boardname.dtb is used.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Tobias Müller <Tobias.Mueller@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

If a DTB is found with cramfsls, the bootscript continues as expected.
If none is found, the cramfsloadfdt and boot subbootcmds are updated to
not load the DTB from cramfs and not pass it to the kernel. The kernel
thus must have an appended DTB otherwise the boot will fail.

This is required for the km_kirkwood boards that must support .esw where
the DTB sometimes is appended (for backwards compatibility) and sometimes
is passed correctly (as we do now for all newer boards).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

To prevent u-boot to stop accidently e.g. due to line noise on the
serial line, we now use the option CONFIG_AUTOBOOT_KEYED. We choose the
<SPACE> key for this.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

There was a small typo for KM_COGE5UN that resulted in the dip switch
not to behave as expected.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

Similar to kmcoge5un we need to check the dip switch at startup
connected to the kirkwood at MPP43. If it's set we need to set the
actual_bank to zero to boot from SW bank zero. Additional to kmcoge5un
we need to check also the pin in misc_init to decide wether we wait for
the ne to start or not. If the dip_switch is set we don't wait and
continue immediately.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

Configure PHY LED register for Marvell 88E1118R PHY used on PIGGY3 to
match with printed descriptions on PCB

Signed-off-by: Tobias Müller <Tobias.Mueller@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[trini: Fix typo, CRTL_PAGE -> CTRL_PAGE]
Signed-off-by: Tom Rini <trini@konsulko.com>

KM_ENV_BUS was used for nothing else than an direct assignment to
CONFIG_I2C_ENV_EEPROM_BUS. To avoid this, directly use
CONFIG_I2C_ENV_EEPROM_BUS instead.

Patchwork: http://patchwork.ozlabs.org/patch/399411/


Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>

SeeedStudio BeagleBone Green (BBG) is clone of the BeagleBone Black (BBB) minus
the HDMI port and addition of two Grove connectors (i2c2 and usart2).

This board can be identified by the 1A value after A335BNLT (BBB) in the at24 eeprom:
1A: [aa 55 33 ee 41 33 33 35  42 4e 4c 54 1a 00 00 00 |.U3.A335BNLT....|]

http://beagleboard.org/green
http://www.seeedstudio.com/wiki/Beaglebone_green

In Mainline Kernel as of:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=79a4e64c679d8a0b1037da174e4aea578c80c4e6



Patch tested on BeagleBone Black (rev C) and BeagleBone Green (production model)

Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Jason Kridner <jkridner@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Add CMD_GPIO to Kconfig and run tools/moveconfig.py .

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>

This updates git-mailrc to add me as a maintainer of x86.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

CM-T3517 has several HW revisions.
Add board specific get_board_rev() callback to retrieve revision number.

Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Igor Grinberg <grinberg@compulab.co.il>

Currently the mmc device that SPL looks at is always mmc0, regardless
of the BOOT_DEVICE_MMCx value. This forces some boards to
implement hacks in order to boot from other mmc devices.

Make SPL take into account the correct mmc device.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>

Use spl alternate boot device feature to define fallback to
the main boot device as it is defined by hardware.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

Now that we support alternative boot devices, it can sometimes be
unclear which boot devices was actually used. Provide a function to
announce which boot devices are attempted during boot.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Introduce spl_boot_list array, which defines a list of boot devices
that SPL will try before hanging. By default this list will consist
of only spl_boot_device(), but board_boot_order() can be overridden
by board code to populate the array with custom values.

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>