Bring in a copyright for this file from cmd/pmic.c since this file was
submitted by the same author at around the same time. Also fix the missing
header guard.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

On recent SoCs, tegra_pcie_phy_enable() isn't called; but instead
tegra_pcie_enable_controller() calls tegra_xusb_phy_enable(). However,
part of tegra_pcie_phy_enable() needs to happen in all cases. Move that
code to tegra_pcie_port_enable() instead.

For reference, NVIDIA's downstream Linux kernel performs this operation
in tegra_pcie_enable_rp_features(), which is called immediately after
tegra_pcie_port_enable(). Since that function doesn't exist in the U-Boot
driver, we'll just add it to the tail of tegra_pcie_port_enable() instead.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

The value that should be programmed into the PADS_REFCLK register varies
per SoC. Fix the Tegra PCIe driver to program the correct values. Future
SoCs will require different values in cfg0/1, so the two values are stored
separately in the per-SoC data structures.

For reference, the values are all documented in NV bug 1771116 comment 20.
The Tegra210 value doesn't match the current TRM, but I've filed a bug to
get the TRM fixed. Earlier TRMs don't document the value this register
should contain, but the ASIC team has validated all these values, except
for the Tegra20 value which is simply left unchanged in this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Currently on attempt to use global_data.h in an assembly file following
will happen:
-------------------->8-----------------
./arch/arc/include/asm/global_data.h: Assembler messages:
./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{'
./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}'
scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed
-------------------->8-----------------

In this change we disable struct arch_global_data in ASM which fixes
the issue above.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Newer ARC toolchains don't support "-marchs" option any longer.
Instead "-mcpu=archs" should be used. What's also important older
toiolchains that support ARC HS cores will also happily accept
"-mcpu=archs" so that's a very safe move.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

The Parrot Board is an evaluation board with an Allwinner R16 (assumed
to be close to an Allwinner A33), 4GB of eMMC, 512MB of RAM, USB host
and OTG, a WiFi/Bluetooth combo chip, a micro SD Card reader, 2
controllable buttons, an LVDS port with separated backlight and
capacitive touch panel ports, an audio/microphone jack, a camera CSI
port, 2 sets of 22 GPIOs and an accelerometer.

The DTS file is identical to the one submitted to the upstream kernel.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Commit b19236fd ("sunxi: Increase SPL header size to 64 bytes to avoid
code corruption") Added defines for MMC0 and SPI as boot identification.
After verifying on an OLinuXino Lime2 with NAND and eMMC, the expected
values have been confirmed and added to spl.h

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

The switch to simple_printf was causing the SPL dram info to show as:

DRAM: u MiB

This fixes this by switching from %lu to %d for printing the DRAM size.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Signed-off-by: Tom Rini <trini@konsulko.com>

Otherwise,  ocassionally see errors like this:
  Flashing sparse image at offset 2078720
  Flashing Sparse Image
  sdhci_send_command: Timeout for status update!
  mmc fail to send stop cmd
  write_sparse_image: Write failed, block #2181088 [0]

This does not affect the actual writing speed, which is controlled by
the default value:
  CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT

It only increases the retries when reading:
  SDHCI_INT_STATUS
to avoid the timeout error.

Signed-off-by: Steve Rae <steve.rae@raedomain.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Jaehoon Chung <jh80.chung@samsung.com>

DRA72-Evm revC uses dra72-evm-revc.dtb. Update the same in env vatiables.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Move the bootdelay >= 0 check to the caller, which simplifies
the callees.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

Factor out the same code from the callees to the caller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

Because abortboot_keyed() and abortboot_normal() are not compiled
at the same time, we can rename both of them to __abortboot().
This allows to drop #ifdef from the caller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

As the help message of CONFIG_BOOTDELAY says, CONFIG_BOOTDELAY=-2
means the autoboot with no delay, with no abort check even if
CONFIG_ZERO_BOOTDELAY_CHECK is defined.

To sum up, the autoboot behaves as follows:

 [1] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=y
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    autoboot with no delay, with no check for abort

 [3] CONFIG_BOOTDELAY=-1
    disable autoboot

 [4] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

As you notice, [2] and [4] come to the same result, which means we
do not need CONFIG_ZERO_BOOTDELAY_CHECK.  We can control all the
cases only by CONFIG_BOOTDELAY, like this:

 [1] CONFIG_BOOTDELAY=0
    autoboot with no delay, but you can abort it by key input

 [2] CONFIG_BOOTDELAY=-1
    disable autoboot

 [3] CONFIG_BOOTDELAY=-2
    autoboot with no delay, with no check for abort

This commit converts the logic as follow:
  CONFIG_BOOTDELAY=0 && CONFIG_ZERO_BOOTDELAY_CHECK=n
    --> CONFIG_BOOTDELAY=-2

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Christian Riesch <christian.riesch@omicronenergy.com>
Acked-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>

The same information now exists in common/Kconfig.  Do not duplicate
documentation from the point of view of maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

This recently added board missed the tree-wide migration of
CONFIG_BOOTDELAY.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>

Align the name of the defconfig file for high-security (HS) device variants
from the AM43xx family of SoCs with the corresponding name used for the
general purpose devices. This allows for easier cross-association of those
files and also provides room to grow from an HS device part number
perspective.

Furthermore, update and cleanup associated MAINTAINERS file.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Madan Srinivas <madans@ti.com>

Correcting QSPI disable/unselect CS reset value.
CTRL_CORE_CONTROL_IO_2: QSPI_MEMMAPPED_CS[10:8]

This is not causing any issue, but its better
to untouch the reserved bits.

Praneeth Bajjuri <praneeth@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>

I will carry this work-around until it is cared in the kernel.
This looks up the AIDET node and sets up a register to handle
active low interrupt signals.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

The AIDET (ARM Interrupt Detector Add-on Circuit) is a kind of
syscon block related with the interrupt controller.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

SPL does not use all of the devices, so we can save some memory
footprint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration
(pin biasing, drive strength control), but not pin-muxing.

Allow to fill the mux value table with -1 for those pins; pins with
mux value -1 will be skipped in the pin-mux set function.  The mux
value type should be changed from "unsigned" to "int" in order to
accommodate -1 as a special case.

[ Linux commit: 363c90e743b50a432a91a211dd8b078d9df446e9 ]

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

PH1-LD11 and PH1-LD20 have much pin controlling in common, so I
added a single driver shared between them in the initial commit.

However, the Ethernet pin-mux settings I am going to add are
different with each other, and they may diverge more as the
progress of development.  Split it into two dedicated drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Currently, the UniPhier pinctrl driver itself is a syscon, but it
turned out much more reasonable to make it a child node of a syscon
because our syscon node consists of a bunch of system configuration
registers, not only pinctrl, but also phy, and misc registers.
It is difficult to split the node.  This commit allows to migrate to
the new DT structure.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

I periodically sync Device Trees for better maintainability.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

This SoC does not support NAND CS1.  This place-holder is no longer
necessary.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

My mistake in the initial support patch.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

These are pin group names, not function names.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

There is a dummy pch driver in the coreboot directory. This causes
drivers of its children fail to function due to empty ops. Remove
the whole file since it is no longer needed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Signed-off-by: Tom Rini <trini@konsulko.com>

Currently layescape SoCs are not using cpu nodes. So removing
them in favour of compatibly with  similar SoCs that
have different cores like LS2080A and LS2088A.

This has been tested on LS2080AQDS, LS1043ARDB, LS1012ARDB.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>