Fixup SGMII PHY ids in the device tree

The device tree's PHY addresses need to be fixed up if we're using the
SGMII Riser Card.

The 8572, 8536, and 8544 DS boards were modified to call this function.

Code idea taken from Liu Yu <yu.liu@freescale.com>

Signed-off-by: Andy Fleming <afleming@freescale.com>

board/freescale/common/sgmii_riser.c

@@ -14,6 +14,8 @@
 
 #include <config.h>
 #include <common.h>
+#include <net.h>
+#include <libfdt.h>
 #include <tsec.h>
 
 void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
@@ -24,3 +26,66 @@ void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
 		if (tsec_info[i].flags & TSEC_SGMII)
 			tsec_info[i].phyaddr += SGMII_RISER_PHY_OFFSET;
 }
+
+void fsl_sgmii_riser_fdt_fixup(void *fdt)
+{
+	struct eth_device *dev;
+	int node;
+	int i = -1;
+	int etsec_num = 0;
+
+	node = fdt_path_offset(fdt, "/aliases");
+	if (node < 0)
+		return;
+
+	while ((dev = eth_get_dev_by_index(++i)) != NULL) {
+		struct tsec_private *priv;
+		int enet_node;
+		char enet[16];
+		const u32 *phyh;
+		int phynode;
+		const char *model;
+		const char *path;
+
+		printf("Updating PHY address for %s\n", dev->name);
+		if (!strstr(dev->name, "eTSEC"))
+			continue;
+
+		sprintf(enet, "ethernet%d", etsec_num++);
+		path = fdt_getprop(fdt, node, enet, NULL);
+		if (!path) {
+			debug("No alias for %s\n", enet);
+			continue;
+		}
+
+		enet_node = fdt_path_offset(fdt, path);
+		if (enet_node < 0)
+			continue;
+
+		model = fdt_getprop(fdt, enet_node, "model", NULL);
+
+		printf("%s's model is %s\n", enet, model);
+		/*
+		 * We only want to do this to eTSECs.  On some platforms
+		 * there are more than one type of gianfar-style ethernet
+		 * controller, and as we are creating an implicit connection
+		 * between ethernet nodes and eTSEC devices, it is best to
+		 * make the connection use as much explicit information
+		 * as exists.
+		 */
+		if (!strstr(model, "TSEC"))
+			continue;
+
+		phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
+		if (!phyh)
+			continue;
+
+		phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh));
+
+		priv = dev->priv;
+
+		printf("Device flags are %x\n", priv->flags);
+		if (priv->flags & TSEC_SGMII)
+			fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
+	}
+}

board/freescale/common/sgmii_riser.h

@@ -13,3 +13,4 @@
  */
 
 void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num);
+void fsl_sgmii_riser_fdt_fixup(void *fdt);

board/freescale/mpc8536ds/mpc8536ds.c

@@ -625,8 +625,10 @@ int board_eth_init(bd_t *bis)
 		return 0;
 	}
 
+#ifdef CONFIG_FSL_SGMII_RISER
 	if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
 		fsl_sgmii_riser_init(tsec_info, num);
+#endif
 
 	tsec_eth_init(bis, tsec_info, num);
 #endif
@@ -653,5 +655,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCIE1
 	ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
 #endif
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
 }
 #endif

board/freescale/mpc8544ds/mpc8544ds.c

@@ -497,5 +497,8 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCIE3
 	ft_fsl_pci_setup(blob, "pci3", &pcie2_hose);
 #endif
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
 }
 #endif

board/freescale/mpc8572ds/mpc8572ds.c

@@ -542,7 +542,9 @@ int board_eth_init(bd_t *bis)
 		return 0;
 	}
 
+#ifdef CONFIG_FSL_SGMII_RISER
 	fsl_sgmii_riser_init(tsec_info, num);
+#endif
 
 	tsec_eth_init(bis, tsec_info, num);
 
@@ -575,6 +577,9 @@ void ft_board_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_PCIE1
 	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 #endif
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
 }
 #endif