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Commit fd45a0d1 authored by Heiko Schocher's avatar Heiko Schocher Committed by Andreas Bießmann
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at91: corvus: board updates


- rename at91_spl_board_init into spl_board_init
- use SZ_1X defines for sizes

Signed-off-by: default avatarHeiko Schocher <hs@denx.de>
parent f0dc73c0
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...@@ -73,7 +73,7 @@ static void corvus_nand_hw_init(void) ...@@ -73,7 +73,7 @@ static void corvus_nand_hw_init(void)
#include <spl.h> #include <spl.h>
#include <nand.h> #include <nand.h>
void at91_spl_board_init(void) void spl_board_init(void)
{ {
/* /*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test * For on the sam9m10g45ek board, the chip wm9711 stay in the test
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#define __CONFIG_H #define __CONFIG_H
#include <asm/hardware.h> #include <asm/hardware.h>
#include <linux/sizes.h>
#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_GENERIC_BOARD
/* /*
...@@ -81,7 +82,7 @@ ...@@ -81,7 +82,7 @@
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR \ #define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE)
/* No NOR flash */ /* No NOR flash */
#define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_NO_FLASH
...@@ -113,13 +114,13 @@ ...@@ -113,13 +114,13 @@
#define CONFIG_DOS_PARTITION #define CONFIG_DOS_PARTITION
#define CONFIG_USB_STORAGE #define CONFIG_USB_STORAGE
#define CONFIG_SYS_LOAD_ADDR 0x72000000 /* load address */ #define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 /* load address */
/* bootstrap + u-boot + env in nandflash */ /* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x100000 #define CONFIG_ENV_OFFSET 0x100000
#define CONFIG_ENV_OFFSET_REDUND 0x180000 #define CONFIG_ENV_OFFSET_REDUND 0x180000
#define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_BOOTCOMMAND \ #define CONFIG_BOOTCOMMAND \
"nand read 0x70000000 0x200000 0x300000;" \ "nand read 0x70000000 0x200000 0x300000;" \
...@@ -146,15 +147,16 @@ ...@@ -146,15 +147,16 @@
* Size of malloc() pool * Size of malloc() pool
*/ */
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
128*1024, 0x1000) SZ_4M, 0x1000)
/* Defines for SPL */ /* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE 0x300000 #define CONFIG_SPL_TEXT_BASE 0x300000
#define CONFIG_SPL_MAX_SIZE (12 * 1024) #define CONFIG_SPL_MAX_SIZE (12 * SZ_1K)
#define CONFIG_SPL_STACK (16 * 1024) #define CONFIG_SPL_STACK (SZ_16K)
#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE #define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
#define CONFIG_SPL_BSS_MAX_SIZE (2 * 1024) #define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K)
#define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT
...@@ -174,8 +176,8 @@ ...@@ -174,8 +176,8 @@
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE) CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
......
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