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Commit fd2b10b6 authored by Michal Simek's avatar Michal Simek
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fpga: zynqpl: Add support for zc7100 device.


- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: default avatarJagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent a78dac79
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...@@ -20,6 +20,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); ...@@ -20,6 +20,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif #endif
int board_init(void) int board_init(void)
...@@ -42,6 +43,9 @@ int board_init(void) ...@@ -42,6 +43,9 @@ int board_init(void)
case XILINX_ZYNQ_7045: case XILINX_ZYNQ_7045:
fpga = fpga045; fpga = fpga045;
break; break;
case XILINX_ZYNQ_7100:
fpga = fpga100;
break;
} }
#endif #endif
......
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#endif #endif
#ifndef CONFIG_SYS_FPGA_PROG_TIME #ifndef CONFIG_SYS_FPGA_PROG_TIME
#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif #endif
int zynq_info(Xilinx_desc *desc) int zynq_info(Xilinx_desc *desc)
......
...@@ -20,12 +20,14 @@ extern int zynq_info(Xilinx_desc *desc); ...@@ -20,12 +20,14 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc #define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7045 0x11 #define XILINX_ZYNQ_7045 0x11
#define XILINX_ZYNQ_7100 0x16
/* Device Image Sizes */ /* Device Image Sizes */
#define XILINX_XC7Z010_SIZE 16669920/8 #define XILINX_XC7Z010_SIZE 16669920/8
#define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8 #define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z045_SIZE 106571232/8
#define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */ /* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \ #define XILINX_XC7Z010_DESC(cookie) \
...@@ -40,4 +42,7 @@ extern int zynq_info(Xilinx_desc *desc); ...@@ -40,4 +42,7 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_XC7Z045_DESC(cookie) \ #define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" } { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
#define XILINX_XC7Z100_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
#endif /* _ZYNQPL_H_ */ #endif /* _ZYNQPL_H_ */
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