clock_imx8mm: use readl_poll_timeout

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

arch/arm/include/asm/arch-imx8m/clock_imx8mm.h

@@ -424,53 +424,6 @@ enum dram_bypassclk_val {
 	DRAM_BYPASSCLK_400M,
 };
 
-#define AUDIO_PLL1_GNRL_CTL			(0x30360000)
-#define AUDIO_PLL1_FDIV_CTL0			(0x30360004)
-#define AUDIO_PLL1_FDIV_CTL1			(0x30360008)
-#define AUDIO_PLL1_SSCG_CTL			(0x3036000c)
-#define AUDIO_PLL1_MNIT_CTL			(0x30360010)
-#define AUDIO_PLL2_GNRL_CTL			(0x30360014)
-#define AUDIO_PLL2_FDIV_CTL0			(0x30360018)
-#define AUDIO_PLL2_FDIV_CTL1			(0x3036001c)
-#define AUDIO_PLL2_SSCG_CTL			(0x30360020)
-#define AUDIO_PLL2_MNIT_CTL			(0x30360024)
-#define VIDEO_PLL1_GNRL_CTL			(0x30360028)
-#define VIDEO_PLL1_FDIV_CTL0			(0x3036002c)
-#define VIDEO_PLL1_FDIV_CTL1			(0x30360030)
-#define VIDEO_PLL1_SSCG_CTL			(0x30360034)
-#define VIDEO_PLL1_MNIT_CTL			(0x30360038)
-#define DRAM_PLL_GNRL_CTL			(0x30360050)
-#define DRAM_PLL_FDIV_CTL0			(0x30360054)
-#define DRAM_PLL_FDIV_CTL1			(0x30360058)
-#define DRAM_PLL_SSCG_CTL			(0x3036005c)
-#define DRAM_PLL_MNIT_CTL			(0x30360060)
-#define GPU_PLL_GNRL_CTL			(0x30360064)
-#define GPU_PLL_DIV_CTL				(0x30360068)
-#define GPU_PLL_LOCKED_CTL			(0x3036006c)
-#define GPU_PLL_MNIT_CTL			(0x30360070)
-#define VPU_PLL_GNRL_CTL			(0x30360074)
-#define VPU_PLL_DIV_CTL				(0x30360078)
-#define VPU_PLL_LOCKED_CTL			(0x3036007c)
-#define VPU_PLL_MNIT_CTL			(0x30360080)
-#define ARM_PLL_GNRL_CTL			(0x30360084)
-#define ARM_PLL_DIV_CTL				(0x30360088)
-#define ARM_PLL_LOCKED_CTL			(0x3036008c)
-#define ARM_PLL_MNIT_CTL			(0x30360090)
-#define SYS_PLL1_GNRL_CTL			(0x30360094)
-#define SYS_PLL1_DIV_CTL			(0x30360098)
-#define SYS_PLL1_LOCKED_CTL			(0x3036009c)
-#define SYS_PLL1_MNIT_CTL			(0x30360100)
-#define SYS_PLL2_GNRL_CTL			(0x30360104)
-#define SYS_PLL2_DIV_CTL			(0x30360108)
-#define SYS_PLL2_LOCKED_CTL			(0x3036010c)
-#define SYS_PLL2_MNIT_CTL			(0x30360110)
-#define SYS_PLL3_GNRL_CTL			(0x30360114)
-#define SYS_PLL3_DIV_CTL			(0x30360118)
-#define SYS_PLL3_LOCKED_CTL			(0x3036011c)
-#define SYS_PLL3_MNIT_CTL			(0x30360120)
-#define ANAMIX_MISC_CTL				(0x30360124)
-#define DIGPROG					(0x30360800)
-
 #define INTPLL_LOCK_MASK			BIT(31)
 #define INTPLL_LOCK_SEL_MASK			BIT(29)
 #define INTPLL_EXT_BYPASS_MASK			BIT(28)

arch/arm/mach-imx/imx8m/clock_imx8mm.c

@@ -331,6 +331,8 @@ int fracpll_configure(enum pll_clocks clock, u32 freq)
 	u32 tmp, div_val;
 	struct ana_grp* pll;
 	struct imx_int_pll_rate_table *rate;
+	u32 val;
+	int ret;
 
 	for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
 		if (freq == imx8mm_fracpll_tbl[i].rate)
@@ -357,7 +359,7 @@ int fracpll_configure(enum pll_clocks clock, u32 freq)
 		pll = &ana_pll->video_pll1;
 		break;
 	default:
-		return 0;
+		return -EINVAL;
 	}
 	/* Bypass clock and set lock to pll output lock */
 	tmp = readl(&pll->gnrl_ctl);
@@ -380,14 +382,15 @@ int fracpll_configure(enum pll_clocks clock, u32 freq)
 	writel(tmp, &pll->gnrl_ctl);
 
 	/* Wait Lock*/
-	while (!(readl(&pll->gnrl_ctl) & LOCK_STATUS))
-		;
+	ret = readl_poll_timeout(&pll->gnrl_ctl, val, val & LOCK_STATUS, 100);
+	if (ret)
+		printf("%s timeout\n", __func__);
 
 	/* Bypass */
 	tmp &= ~BYPASS_MASK;
 	writel(tmp, &pll->gnrl_ctl);
 
-	return 0;
+	return ret;
 }
 
 void dram_pll_init(enum dram_pll_out_val pll_val)
@@ -452,6 +455,8 @@ int intpll_configure(enum pll_clocks clock, enum intpll_out_freq freq)
 {
 	struct ana_grp2 *pll;
 	u32 div_ctl_val, pll_clke_masks;
+	u32 val;
+	int ret;
 
 	switch (clock) {
 	case ANATOP_SYSTEM_PLL1:
@@ -531,13 +536,15 @@ int intpll_configure(enum pll_clocks clock, enum intpll_out_freq freq)
 	/* Disable reset */
 	setbits_le32(&pll->gnrl_ctl, INTPLL_RST_MASK);
 	/* Wait Lock */
-	while (!(readl(&pll->gnrl_ctl) & INTPLL_LOCK_MASK))
-		;
+	ret = readl_poll_timeout(&pll->gnrl_ctl, val, val & INTPLL_LOCK_MASK, 100);
+	if (ret)
+		printf("%s timeout\n", __func__);
+
 	/* Clear bypass */
 	clrbits_le32(&pll->gnrl_ctl, INTPLL_BYPASS_MASK);
 	setbits_le32(&pll->gnrl_ctl, pll_clke_masks);
 
-	return 0;
+	return ret;
 }
 
 void enable_display_clk(unsigned char enable)
@@ -570,36 +577,35 @@ int clock_init(void)
 	uint32_t val_cfg0;
 
 	/* Configure ARM at 1GHz */
-	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
+	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
 			     CLK_ROOT_SOURCE_SEL(0));
 
 	intpll_configure(ANATOP_ARM_PLL, INTPLL_OUT_1200M);
 
-	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | \
-			     CLK_ROOT_SOURCE_SEL(1) | \
+	clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1) |
 			     CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
-
 	/*
 	 * According to ANAMIX SPEC
 	 * sys pll1 fixed at 800MHz
 	 * sys pll2 fixed at 1GHz
 	 * Here we only enable the outputs.
 	 */
-	val_cfg0 = readl(SYS_PLL1_GNRL_CTL);
+	val_cfg0 = readl(&ana_pll->sys_pll1.gnrl_ctl);
 	val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 		INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 		INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 		INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 		INTPLL_DIV20_CLKE_MASK;
-	writel(val_cfg0, SYS_PLL1_GNRL_CTL);
+	writel(val_cfg0, &ana_pll->sys_pll1.gnrl_ctl);
 
-	val_cfg0 = readl(SYS_PLL2_GNRL_CTL);
+	val_cfg0 = readl(&ana_pll->sys_pll2.gnrl_ctl);
 	val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
 		INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
 		INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
 		INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
 		INTPLL_DIV20_CLKE_MASK;
-	writel(val_cfg0, SYS_PLL2_GNRL_CTL);
+	writel(val_cfg0, &ana_pll->sys_pll2.gnrl_ctl);
 
 	intpll_configure(ANATOP_SYSTEM_PLL3, INTPLL_OUT_750M);
 	clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2));