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Commit f73db66d authored by Simon Glass's avatar Simon Glass Committed by Tom Rini
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arm: Remove tk71 board 


This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
parent 7650beb7
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arch/arm/mach-kirkwood/Kconfig
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...@@ -25,9 +25,6 @@ config TARGET_DNS325 ...@@ -25,9 +25,6 @@ config TARGET_DNS325
config TARGET_ICONNECT config TARGET_ICONNECT
bool "iconnect Board" bool "iconnect Board"
config TARGET_TK71
bool "TK71 Board"
config TARGET_KM_KIRKWOOD config TARGET_KM_KIRKWOOD
bool "KM_KIRKWOOD Board" bool "KM_KIRKWOOD Board"
...@@ -64,7 +61,6 @@ source "board/buffalo/lsxl/Kconfig" ...@@ -64,7 +61,6 @@ source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig" source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig" source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig" source "board/iomega/iconnect/Kconfig"
source "board/karo/tk71/Kconfig"
source "board/keymile/km_arm/Kconfig" source "board/keymile/km_arm/Kconfig"
source "board/LaCie/net2big_v2/Kconfig" source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig" source "board/LaCie/netspace_v2/Kconfig"
......
board/karo/tk71/Kconfig deleted 100644 → 0
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if TARGET_TK71
config SYS_BOARD
default "tk71"
config SYS_VENDOR
default "karo"
config SYS_CONFIG_NAME
default "tk71"
endif
board/karo/tk71/MAINTAINERS deleted 100644 → 0
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TK71 BOARD
#M: -
S: Maintained
F: board/karo/tk71/
F: include/configs/tk71.h
F: configs/tk71_defconfig
board/karo/tk71/Makefile deleted 100644 → 0
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#
# Copyright (C) 2012 Marek Vasut <marex@denx.de>
# on behalf of DENX Software Engineering GmbH
#
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := tk71.o
board/karo/tk71/kwbimage.cfg deleted 100644 → 0
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#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# adopted to TK71 by
# Nils Faerber <nils.faerber@kernelconcepts.de>
#
# SPDX-License-Identifier: GPL-2.0+
#
# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000034 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x00000000 # DDR Address Control
# bit1-0: 01, Cs0width=x16
# bit3-2: 10, Cs0size=512Mb
# bit5-4: 01, Cs1width=x16
# bit7-6: 10, Cs1size=512Mb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000652 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000042 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 0, DDR drive strenght normal
# bit2: 0, DDR ODT control lsd (disabled)
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, (disabled)
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low)
# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
# bit3-2: 01, ODT1 active NEVER!
# bit31-4: zero, required
DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
# bit14: 1, M_STARTBURST_IN ODT: Enabled
# bit15: 1, DDR IO ODT Unit: Use ODT block
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0
board/karo/tk71/tk71.c deleted 100644 → 0
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/*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
* on behalf of DENX Software Engineering GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <miiphy.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#define TK71_OE_LOW (~0)
#define TK71_OE_HIGH (~0)
#define TK71_OE_VAL_LOW (0)
#define TK71_OE_VAL_HIGH (0)
int board_early_init_f(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
mvebu_config_gpio(TK71_OE_VAL_LOW,
TK71_OE_VAL_HIGH,
TK71_OE_LOW, TK71_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_SD_CLK,
MPP13_SD_CMD,
MPP14_SD_D0,
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP28_GPIO,
MPP29_GPIO,
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP34_GPIO,
MPP35_GPIO,
MPP36_GPIO,
MPP37_GPIO,
MPP38_GPIO,
MPP39_GPIO,
MPP40_GPIO,
MPP41_GPIO,
MPP42_GPIO,
MPP43_GPIO,
MPP44_GPIO,
MPP45_GPIO,
MPP46_GPIO,
MPP47_GPIO,
MPP48_GPIO,
MPP49_GPIO,
0
};
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
int board_init(void)
{
/*
* arch number of board
*/
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
#ifdef CONFIG_CMD_NET
#define MV88E1116_MAC_CTRL2_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
static void mv_phy_88e1118_init(char *name)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1118 Initialized on %s\n", name);
}
/* Configure and enable Switch and PHY */
void reset_phy(void)
{
/* configure and initialize PHY */
mv_phy_88e1118_init("egiga0");
}
#endif
configs/tk71_defconfig deleted 100644 → 0
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CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_TK71=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
include/configs/tk71.h deleted 100644 → 0
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/*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
* on behalf of DENX Software Engineering GmbH
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_TK71_H__
#define __CONFIG_TK71_H__
/*
* Version number information
*/
#define CONFIG_IDENT_STRING "\nKa-Ro TK71"
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_NR_DRAM_BANKS 1
#define MACH_TYPE_TK71 2399
#define CONFIG_MACH_TYPE MACH_TYPE_TK71
/*
* Commands configuration
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* NAND flash
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV "nand0,3"
#endif
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0}
#define CONFIG_PHY_BASE_ADR 0x08
#endif
/*
* USB/EHCI
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_KIRKWOOD
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#endif
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SECT_SIZE 0x20000
#else
#define CONFIG_ENV_IS_NOWHERE
#endif
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_ADDR 0x80000
#define CONFIG_ENV_OFFSET 0x80000
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;"
#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)"
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \
"update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \
"update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \
"update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \
"mtdids=nand0=orion_nand\0" \
"mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \
"bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0"
#define MTDIDS_DEFAULT "nand0=orion_nand"
#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS
#define PHYS_SDRAM_1 0x00000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */
#endif /* __CONFIG_TK71_H__ */
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