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Commit eed7c0f7 authored by SRICHARAN R's avatar SRICHARAN R Committed by Tom Rini
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ARM: OMAP5: Add silicon id support for ES2.0 revision.


Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.

Signed-off-by: default avatarR Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>
parent ef1697e9
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...@@ -204,17 +204,22 @@ void init_omap_revision(void) ...@@ -204,17 +204,22 @@ void init_omap_revision(void)
*/ */
unsigned int rev = cortex_rev(); unsigned int rev = cortex_rev();
switch (rev) { switch (readl(CONTROL_ID_CODE)) {
case MIDR_CORTEX_A15_R0P0: case OMAP5430_CONTROL_ID_CODE_ES1_0:
switch (readl(CONTROL_ID_CODE)) { *omap_si_rev = OMAP5430_ES1_0;
case OMAP5430_CONTROL_ID_CODE_ES1_0: if (rev == MIDR_CORTEX_A15_R2P2)
*omap_si_rev = OMAP5430_ES1_0; *omap_si_rev = OMAP5430_ES2_0;
break; break;
case OMAP5432_CONTROL_ID_CODE_ES1_0: case OMAP5432_CONTROL_ID_CODE_ES1_0:
default: *omap_si_rev = OMAP5432_ES1_0;
*omap_si_rev = OMAP5432_ES1_0; if (rev == MIDR_CORTEX_A15_R2P2)
break; *omap_si_rev = OMAP5432_ES2_0;
} break;
case OMAP5430_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5430_ES2_0;
break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
*omap_si_rev = OMAP5432_ES2_0;
break; break;
default: default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID; *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
......
...@@ -57,7 +57,9 @@ ...@@ -57,7 +57,9 @@
/* To be verified */ /* To be verified */
#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
/* STD_FUSE_PROD_ID_1 */ /* STD_FUSE_PROD_ID_1 */
#define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
......
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
/* Cortex-A15 revisions */ /* Cortex-A15 revisions */
#define MIDR_CORTEX_A15_R0P0 0x410FC0F0 #define MIDR_CORTEX_A15_R0P0 0x410FC0F0
#define MIDR_CORTEX_A15_R2P2 0x412FC0F2
/* CCSIDR */ /* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0 #define CCSIDR_LINE_SIZE_OFFSET 0
......
...@@ -542,4 +542,6 @@ static inline u32 omap_revision(void) ...@@ -542,4 +542,6 @@ static inline u32 omap_revision(void)
#define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_SILICON_ID_INVALID 0
#define OMAP5430_ES1_0 0x54300100 #define OMAP5430_ES1_0 0x54300100
#define OMAP5432_ES1_0 0x54320100 #define OMAP5432_ES1_0 0x54320100
#define OMAP5430_ES2_0 0x54300200
#define OMAP5432_ES2_0 0x54320200
#endif /* _OMAP_COMMON_H_ */ #endif /* _OMAP_COMMON_H_ */
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