[MIPS] <asm/mipsregs.h>: Update coprocessor register access macros

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

board/dbau1x00/dbau1x00.c

@@ -52,7 +52,7 @@ int checkboard (void)
 
 	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
 
-	proc_id = read_32bit_cp0_register(CP0_PRID);
+	proc_id = read_c0_prid();
 
 	switch (proc_id >> 24) {
 	case 0:

board/gth2/gth2.c

@@ -135,7 +135,7 @@ int checkboard (void)
 
 	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
 
-	proc_id = read_32bit_cp0_register(CP0_PRID);
+	proc_id = read_c0_prid();
 
 	switch (proc_id >> 24) {
 	case 0:

board/pb1x00/pb1x00.c

@@ -51,7 +51,7 @@ int checkboard (void)
 
 	*sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
 
-	proc_id = read_32bit_cp0_register(CP0_PRID);
+	proc_id = read_c0_prid();
 
 	switch (proc_id >> 24) {
 	case 0:

board/qemu-mips/qemu-mips.c

@@ -38,7 +38,7 @@ int checkboard(void)
 	u32 proc_id;
 	u32 config1;
 
-	proc_id = read_32bit_cp0_register(CP0_PRID);
+	proc_id = read_c0_prid();
 	printf("Board: Qemu -M mips CPU: ");
 	switch (proc_id) {
 	case 0x00018000:
@@ -51,7 +51,7 @@ int checkboard(void)
 		printf("4KEc");
 		break;
 	case 0x00019300:
-		config1 = read_mips32_cp0_config1();
+		config1 = read_c0_config1();
 		if (config1 & 1)
 			printf("24Kf");
 		else
@@ -64,7 +64,7 @@ int checkboard(void)
 		printf("R4000");
 		break;
 	case 0x00018100:
-		config1 = read_mips32_cp0_config1();
+		config1 = read_c0_config1();
 		if (config1 & 1)
 			printf("5Kf");
 		else

cpu/mips/cpu.c

@@ -66,10 +66,10 @@ void flush_cache(ulong start_addr, ulong size)
 
 void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
 {
-	write_32bit_cp0_register(CP0_ENTRYLO0, low0);
-	write_32bit_cp0_register(CP0_PAGEMASK, pagemask);
-	write_32bit_cp0_register(CP0_ENTRYLO1, low1);
-	write_32bit_cp0_register(CP0_ENTRYHI, hi);
-	write_32bit_cp0_register(CP0_INDEX, index);
+	write_c0_entrylo0(low0);
+	write_c0_pagemask(pagemask);
+	write_c0_entrylo1(low1);
+	write_c0_entryhi(hi);
+	write_c0_index(index);
 	tlb_write_indexed();
 }