85xx: fix the wrong DDR settings for MPC8572DS

The default DDR freq is 400MHz or 800M data rate,
the old settings is pure wrong for the default case.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

include/configs/MPC8572DS.h

@@ -115,22 +115,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
 
 /* These are used when DDR doesn't use SPD.  */
-#define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3	0x00000000
-#define CONFIG_SYS_DDR_TIMING_0	0x00260802
-#define CONFIG_SYS_DDR_TIMING_1	0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2		0x062874cf
+#define CONFIG_SYS_DDR_MODE_1		0x00440462
 #define CONFIG_SYS_DDR_MODE_2		0x00000000
-#define CONFIG_SYS_DDR_INTERVAL	0x06180100
+#define CONFIG_SYS_DDR_INTERVAL		0x0c300100
 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
-#define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2	0x04400010
+#define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400000
 
 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000