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Commit db9e5e63 authored by Akshay Saraswat's avatar Akshay Saraswat Committed by Minkyu Kang
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Exynos: clock: Fix a bug in PLL lock check condition


The condition for testing of PLL getting locked was incorrect. Rectify
this error in this patch.

Reported-by: default avatarAlexei Fedorov <alexie.fedorov@arm.com>
Signed-off-by: default avatarHatim Ali <hatim.rv@samsung.com>
Signed-off-by: default avatarAkshay Saraswat <akshay.s@samsung.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
parent dc993a65
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...@@ -494,35 +494,35 @@ void system_clock_init() ...@@ -494,35 +494,35 @@ void system_clock_init()
val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
arm_clk_ratio->apll_sdiv); arm_clk_ratio->apll_sdiv);
writel(val, &clk->apll_con0); writel(val, &clk->apll_con0);
while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
; ;
/* Set MPLL */ /* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1); writel(MPLL_CON1_VAL, &clk->mpll_con1);
val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
writel(val, &clk->mpll_con0); writel(val, &clk->mpll_con0);
while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
; ;
/* Set BPLL */ /* Set BPLL */
writel(BPLL_CON1_VAL, &clk->bpll_con1); writel(BPLL_CON1_VAL, &clk->bpll_con1);
val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
writel(val, &clk->bpll_con0); writel(val, &clk->bpll_con0);
while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
; ;
/* Set CPLL */ /* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1); writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
writel(val, &clk->cpll_con0); writel(val, &clk->cpll_con0);
while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
; ;
/* Set GPLL */ /* Set GPLL */
writel(GPLL_CON1_VAL, &clk->gpll_con1); writel(GPLL_CON1_VAL, &clk->gpll_con1);
val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
writel(val, &clk->gpll_con0); writel(val, &clk->gpll_con0);
while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
; ;
/* Set EPLL */ /* Set EPLL */
...@@ -530,7 +530,7 @@ void system_clock_init() ...@@ -530,7 +530,7 @@ void system_clock_init()
writel(EPLL_CON1_VAL, &clk->epll_con1); writel(EPLL_CON1_VAL, &clk->epll_con1);
val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
writel(val, &clk->epll_con0); writel(val, &clk->epll_con0);
while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
; ;
/* Set VPLL */ /* Set VPLL */
...@@ -538,7 +538,7 @@ void system_clock_init() ...@@ -538,7 +538,7 @@ void system_clock_init()
writel(VPLL_CON1_VAL, &clk->vpll_con1); writel(VPLL_CON1_VAL, &clk->vpll_con1);
val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
writel(val, &clk->vpll_con0); writel(val, &clk->vpll_con0);
while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
; ;
writel(CLK_SRC_CORE0_VAL, &clk->src_core0); writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
......
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