Commit da91cfed authored 8 years ago by Stefan Agner Committed by Tom Rini 8 years ago

ARM: non-sec: flush code cacheline aligned


Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>

parent 2651a052

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