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Commit d8e5163a authored by Shengzhou Liu's avatar Shengzhou Liu Committed by York Sun
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drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl


The clk_adjust is of SDRAM_CLK_CNTL[5:8] 4-bits on MPC85xx and P-series,
but is of SDRAM_CLK_CNTL[5:9] 5-bits on T-series and LS-series SoCs.
We should update it to adapt the case that clk_adjust is odd data.

Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: default avatarYork Sun <york.sun@nxp.com>
parent 8b528709
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...@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, ...@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
/* Per FSL Application Note: AN2805 */ /* Per FSL Application Note: AN2805 */
ss_en = 1; ss_en = 1;
#endif #endif
clk_adjust = popts->clk_adjust; if (fsl_ddr_get_version(0) >= 0x40701) {
/* clk_adjust in 5-bits on T-series and LS-series */
clk_adjust = (popts->clk_adjust & 0x1F) << 22;
} else {
/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
clk_adjust = (popts->clk_adjust & 0xF) << 23;
}
ddr->ddr_sdram_clk_cntl = (0 ddr->ddr_sdram_clk_cntl = (0
| ((ss_en & 0x1) << 31) | ((ss_en & 0x1) << 31)
| ((clk_adjust & 0xF) << 23) | clk_adjust
); );
debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl); debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
} }
......
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