imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL

Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

arch/arm/include/asm/arch-mx6/imx-regs.h

@@ -9,7 +9,11 @@
 
 #define ARCH_MXC
 
+#ifdef CONFIG_MX6UL
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#else
 #define CONFIG_SYS_CACHELINE_SIZE	32
+#endif
 
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF