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Commit cf88affa authored by Masahiro Yamada's avatar Masahiro Yamada
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ARM: uniphier: parse device tree to determine DRAM base and size


Device tree specifies the available memory ranges in its "/memory"
node.  Use it to simplify the CONFIG defines.

Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 9628afa7
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...@@ -18,15 +18,3 @@ int board_init(void) ...@@ -18,15 +18,3 @@ int board_init(void)
return 0; return 0;
} }
#if CONFIG_NR_DRAM_BANKS >= 2
void dram_init_banksize(void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
}
#endif
/* /*
* Copyright (C) 2012-2015 Panasonic Corporation * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include <common.h> #include <common.h>
#include <libfdt.h>
#include <linux/err.h>
DECLARE_GLOBAL_DATA_PTR;
static const void *get_memory_reg_prop(const void *fdt, int *lenp)
{
int offset;
offset = fdt_path_offset(fdt, "/memory");
if (offset < 0)
return NULL;
return fdt_getprop(fdt, offset, "reg", lenp);
}
int dram_init(void) int dram_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; const fdt32_t *val;
gd->ram_size = CONFIG_SYS_SDRAM_SIZE; int len;
val = get_memory_reg_prop(gd->fdt_blob, &len);
if (len < sizeof(*val))
return -EINVAL;
gd->ram_size = fdt32_to_cpu(*(val + 1));
debug("DRAM size = %08lx\n", gd->ram_size);
return 0; return 0;
} }
void dram_init_banksize(void)
{
const fdt32_t *val;
int len, i;
val = get_memory_reg_prop(gd->fdt_blob, &len);
if (len < 0)
return;
len /= sizeof(*val);
len /= 2;
for (i = 0; i < len; i++) {
gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
debug("DRAM bank %d: start = %08lx, size = %08lx\n",
i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
}
}
...@@ -295,17 +295,8 @@ ...@@ -295,17 +295,8 @@
/* Open Firmware flat tree */ /* Open Firmware flat tree */
#define CONFIG_OF_LIBFDT #define CONFIG_OF_LIBFDT
/* Memory Size & Mapping */ #define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE
/* Thre is no memory hole */
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE)
#else
#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE)
#endif
#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
defined(CONFIG_MACH_PH1_SLD8) defined(CONFIG_MACH_PH1_SLD8)
......
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