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Commit bbc5b36b authored by Stephen Warren's avatar Stephen Warren Committed by Tom Warren
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pci: tegra: port to standard clock/reset/pwr domain APIs


Tegra186 supports the new standard clock, reset, and power domain APIs.
Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so
that it can operate with either set of APIs.

On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming.
Consequently, this logic is disabled too.

Signed-off-by: default avatarStephen Warren <swarren@nvidia.com>
Reviewed-by: default avatarSimon Glass <sjg@chromium.org>
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
parent c0493076
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