Skip to content
Snippets Groups Projects
Commit b8e59974 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-x86

parents bff97dde 9532fe3b
No related branches found
No related tags found
No related merge requests found
Showing
with 268 additions and 10 deletions
if TARGET_SOM_DB5800_SOM_6867
config SYS_BOARD
default "som-db5800-som-6867"
config SYS_VENDOR
default "advantech"
config SYS_SOC
default "baytrail"
config SYS_CONFIG_NAME
default "som-db5800-som-6867"
config SYS_TEXT_BASE
default 0xfff00000 if !EFI_STUB
default 0x01110000 if EFI_STUB
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR if !EFI_STUB
select INTEL_BAYTRAIL
select BOARD_ROMSIZE_KB_8192
config PCIE_ECAM_BASE
default 0xe0000000
endif
Advantech SOM-DB5800-SOM-6867
M: George McCollister <george.mccollister@gmail.com>
S: Maintained
F: board/advantech/som-db5800-som-6867
F: include/configs/som-db5800-som-6867.h
F: configs/som-db5800-som-6867_defconfig
F: arch/x86/dts/baytrail_som-db5800-som-6867.dts
#
# Copyright (C) 2015, Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += som-db5800-som-6867.o start.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/* Power Button */
Device (PWRB)
{
Name(_HID, EISAID("PNP0C0C"))
}
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
{
/* platform specific */
#include <asm/arch/acpi/platform.asl>
/* board specific */
#include "acpi/mainboard.asl"
}
/*
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
* Copyright (C) 2016 George McCollister <george.mccollister@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int board_early_init_f(void)
{
/*
* The FSP enables the BayTrail internal legacy UART (again).
* Disable it again, so that the one on the EC can be used.
*/
setup_internal_uart(0);
return 0;
}
int arch_early_init_r(void)
{
return 0;
}
/*
* Copyright (C) 2015, Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
.globl early_board_init
early_board_init:
jmp early_board_init_ret
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
int board_early_init_f(void) int board_early_init_f(void)
{ {
#ifndef CONFIG_INTERNAL_UART
/* /*
* The FSP enables the BayTrail internal legacy UART (again). * The FSP enables the BayTrail internal legacy UART (again).
* Disable it again, so that the Winbond one can be used. * Disable it again, so that the Winbond one can be used.
...@@ -21,6 +22,7 @@ int board_early_init_f(void) ...@@ -21,6 +22,7 @@ int board_early_init_f(void)
/* Enable the legacy UART in the Winbond W83627 Super IO chip */ /* Enable the legacy UART in the Winbond W83627 Super IO chip */
winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
UART0_BASE, UART0_IRQ); UART0_BASE, UART0_IRQ);
#endif
return 0; return 0;
} }
......
...@@ -2,6 +2,7 @@ CONFIG_X86=y ...@@ -2,6 +2,7 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="bayleybay" CONFIG_DEFAULT_DEVICE_TREE="bayleybay"
CONFIG_TARGET_BAYLEYBAY=y CONFIG_TARGET_BAYLEYBAY=y
CONFIG_INTERNAL_UART=y
CONFIG_HAVE_INTEL_ME=y CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y CONFIG_SMP=y
......
CONFIG_X86=y
CONFIG_VENDOR_CONGATEC=y
CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
CONFIG_INTERNAL_UART=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_WINBOND_W83627=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_114=y
CONFIG_USE_PRIVATE_LIBGCC=y
...@@ -2,6 +2,7 @@ CONFIG_X86=y ...@@ -2,6 +2,7 @@ CONFIG_X86=y
CONFIG_VENDOR_INTEL=y CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_DEFAULT_DEVICE_TREE="minnowmax"
CONFIG_TARGET_MINNOWMAX=y CONFIG_TARGET_MINNOWMAX=y
CONFIG_INTERNAL_UART=y
CONFIG_HAVE_INTEL_ME=y CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y CONFIG_SMP=y
......
CONFIG_X86=y
CONFIG_VENDOR_ADVANTECH=y
CONFIG_DEFAULT_DEVICE_TREE="baytrail_som-db5800-som-6867"
CONFIG_TARGET_SOM_DB5800_SOM_6867=y
CONFIG_HAVE_INTEL_ME=y
CONFIG_ENABLE_MRC_CACHE=y
CONFIG_SMP=y
CONFIG_HAVE_VGA_BIOS=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_ACPI_TABLE=y
CONFIG_SEABIOS=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_MMC is not set
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
CONFIG_CMD_PING=y
CONFIG_CMD_TIME=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
CONFIG_USE_PRIVATE_LIBGCC=y
...@@ -1020,8 +1020,6 @@ Features not supported so far (to make it a complete ACPI solution): ...@@ -1020,8 +1020,6 @@ Features not supported so far (to make it a complete ACPI solution):
* S3 (Suspend to RAM), S4 (Suspend to Disk). * S3 (Suspend to RAM), S4 (Suspend to Disk).
Features that are optional: Features that are optional:
* ACPI global NVS support. We may need it to simplify ASL code logic if
utilizing NVS variables. Most likely we will need this sooner or later.
* Dynamic AML bytecodes insertion at run-time. We may need this to support * Dynamic AML bytecodes insertion at run-time. We may need this to support
SSDT table generation and DSDT fix up. SSDT table generation and DSDT fix up.
* SMI support. Since U-Boot is a modern bootloader, we don't want to bring * SMI support. Since U-Boot is a modern bootloader, we don't want to bring
......
...@@ -39,14 +39,9 @@ __weak bool board_should_run_oprom(struct udevice *dev) ...@@ -39,14 +39,9 @@ __weak bool board_should_run_oprom(struct udevice *dev)
return true; return true;
} }
static bool should_load_oprom(struct udevice *dev) __weak bool board_should_load_oprom(struct udevice *dev)
{ {
if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) return true;
return 1;
if (board_should_run_oprom(dev))
return 1;
return 0;
} }
__weak uint32_t board_map_oprom_vendev(uint32_t vendev) __weak uint32_t board_map_oprom_vendev(uint32_t vendev)
...@@ -278,7 +273,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), ...@@ -278,7 +273,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void),
return -ENODEV; return -ENODEV;
} }
if (!should_load_oprom(dev)) if (!board_should_load_oprom(dev))
return -ENXIO; return -ENXIO;
ret = pci_rom_probe(dev, &rom); ret = pci_rom_probe(dev, &rom);
......
/*
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* board/config.h - configuration options, board specific
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd,vga\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x006ef000
#endif /* __CONFIG_H */
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment