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Commit b3e69f41 authored by Troy Kisky's avatar Troy Kisky
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nitrogen8mm: spl: combine pads into 1 array

parent 8f257b30
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...@@ -91,7 +91,7 @@ struct i2c_pads_info i2c_pad_info1[] = { ...@@ -91,7 +91,7 @@ struct i2c_pads_info i2c_pad_info1[] = {
PAD_CTL_FSEL2) PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) #define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
static iomux_v3_cfg_t const usdhc1_pads[] = { static iomux_v3_cfg_t const init_pads[] = {
IOMUX_PAD_CTRL(SD1_CLK__USDHC1_CLK, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD1_CLK__USDHC1_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD1_CMD__USDHC1_CMD, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD1_CMD__USDHC1_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD1_DATA0__USDHC1_DATA0, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD1_DATA0__USDHC1_DATA0, USDHC_PAD_CTRL),
...@@ -104,9 +104,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { ...@@ -104,9 +104,7 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
IOMUX_PAD_CTRL(SD1_DATA7__USDHC1_DATA7, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD1_DATA7__USDHC1_DATA7, USDHC_PAD_CTRL),
#define GP_EMMC_RESET IMX_GPIO_NR(2, 10) #define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
IOMUX_PAD_CTRL(SD1_RESET_B__GPIO2_IO10, 0x41), IOMUX_PAD_CTRL(SD1_RESET_B__GPIO2_IO10, 0x41),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PAD_CTRL(SD2_CLK__USDHC2_CLK, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD2_CLK__USDHC2_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_CMD__USDHC2_CMD, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD2_CMD__USDHC2_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_DATA0__USDHC2_DATA0, USDHC_PAD_CTRL), IOMUX_PAD_CTRL(SD2_DATA0__USDHC2_DATA0, USDHC_PAD_CTRL),
...@@ -116,7 +114,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { ...@@ -116,7 +114,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PAD_CTRL(SD2_RESET_B__GPIO2_IO19, USDHC_GPIO_PAD_CTRL), IOMUX_PAD_CTRL(SD2_RESET_B__GPIO2_IO19, USDHC_GPIO_PAD_CTRL),
#define GP_USDHC2_VSEL IMX_GPIO_NR(3, 2) #define GP_USDHC2_VSEL IMX_GPIO_NR(3, 2)
IOMUX_PAD_CTRL(NAND_CE1_B__GPIO3_IO2, 0x16), IOMUX_PAD_CTRL(NAND_CE1_B__GPIO3_IO2, 0x16),
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) #define GP_USDHC2_CD IMX_GPIO_NR(2, 12)
IOMUX_PAD_CTRL(SD2_CD_B__GPIO2_IO12, USDHC_GPIO_PAD_CTRL), IOMUX_PAD_CTRL(SD2_CD_B__GPIO2_IO12, USDHC_GPIO_PAD_CTRL),
}; };
...@@ -138,8 +136,6 @@ int board_mmc_init(bd_t *bis) ...@@ -138,8 +136,6 @@ int board_mmc_init(bd_t *bis)
switch (i) { switch (i) {
case 0: case 0:
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
imx_iomux_v3_setup_multiple_pads(
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_request(GP_EMMC_RESET, "emmc_reset"); gpio_request(GP_EMMC_RESET, "emmc_reset");
gpio_direction_output(GP_EMMC_RESET, 0); gpio_direction_output(GP_EMMC_RESET, 0);
udelay(500); udelay(500);
...@@ -147,10 +143,8 @@ int board_mmc_init(bd_t *bis) ...@@ -147,10 +143,8 @@ int board_mmc_init(bd_t *bis)
break; break;
case 1: case 1:
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
imx_iomux_v3_setup_multiple_pads( gpio_request(GP_USDHC2_CD, "usdhc2 cd");
usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); gpio_direction_input(GP_USDHC2_CD);
gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
gpio_direction_input(USDHC2_CD_GPIO);
break; break;
default: default:
printf("Warning: you configured more USDHC controllers" printf("Warning: you configured more USDHC controllers"
...@@ -175,7 +169,7 @@ int board_mmc_getcd(struct mmc *mmc) ...@@ -175,7 +169,7 @@ int board_mmc_getcd(struct mmc *mmc)
case USDHC1_BASE_ADDR: case USDHC1_BASE_ADDR:
return 1; return 1;
case USDHC2_BASE_ADDR: case USDHC2_BASE_ADDR:
ret = gpio_get_value(USDHC2_CD_GPIO); ret = gpio_get_value(GP_USDHC2_CD);
return ret ? 0 : 1; return ret ? 0 : 1;
} }
printf("c\n"); printf("c\n");
...@@ -222,8 +216,6 @@ int power_init_boundary(void) ...@@ -222,8 +216,6 @@ int power_init_boundary(void)
gpio_request(GP_USDHC2_VSEL, "usdhc2_vsel"); gpio_request(GP_USDHC2_VSEL, "usdhc2_vsel");
gpio_direction_output(GP_USDHC2_VSEL, 0); gpio_direction_output(GP_USDHC2_VSEL, 0);
imx_iomux_v3_setup_multiple_pads(
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
return ret; return ret;
} }
...@@ -275,6 +267,7 @@ void board_init_f(ulong dummy) ...@@ -275,6 +267,7 @@ void board_init_f(ulong dummy)
} }
enable_tzc380(); enable_tzc380();
imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
for (i = 0; i < ARRAY_SIZE(i2c_pad_info1); i++) for (i = 0; i < ARRAY_SIZE(i2c_pad_info1); i++)
setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1[i]); setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1[i]);
......
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