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Commit b17a1f63 authored by Gary Bisson's avatar Gary Bisson Committed by Troy Kisky
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acl: initial addition, Boundary Devices board 


acl: update to v2017.01
acl update to v2017.03
acl: fix scanner gpios initialization

Signed-off-by: default avatarGary Bisson <gary.bisson@boundarydevices.com>

acl: acl_q2g_defconfig add CONFIG_BLOCK_CACHE
acl_s512m: acl_s512m_defconfig add CONFIG_BLOCK_CACHE
acl: use common code for eth init
acl: eth.c now in common directory
acl: move misc_init_r/do_kbd to common
acl: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common
acl: calibrate 512m Solo board
acl: use common 1066mhz_4x256mx16.cfg
acl: add  CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs
acl: 800mhz_2x128mx16.cfg: remove _P1 accesses
acl: 800mhz_2x128mx16.cfg: use common values

CFG0: 0x40435323 to 0x3f435333
tRFC - 65 to 64 clocks
tFAW - 19 to 20 clocks

CFG1: 0xB66E8D63 to 0xb68e8b63
tRC from 20 to 21 clocks
tWR from 7 to 6 clocks

MR0: 0x13208030 to 0x15208030
tWR from 5 to 6 clocks

acl: use common ddr scripts
acl: port to v2018.07

Signed-off-by: default avatarTroy Kisky <troy.kisky@boundarydevices.com>
parent 5f0bf994
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arch/arm/mach-imx/mx6/Kconfig
+ 4
− 0
View file @ b17a1f63
...@@ -359,6 +359,9 @@ config TARGET_MX6ULL_14X14_EVK ...@@ -359,6 +359,9 @@ config TARGET_MX6ULL_14X14_EVK
config TARGET_A config TARGET_A
bool "a" bool "a"
config TARGET_ACL
bool "acl"
config TARGET_NITROGEN6X config TARGET_NITROGEN6X
bool "nitrogen6x" bool "nitrogen6x"
imply USB_HOST_ETHER imply USB_HOST_ETHER
...@@ -501,6 +504,7 @@ source "board/bachmann/ot1200/Kconfig" ...@@ -501,6 +504,7 @@ source "board/bachmann/ot1200/Kconfig"
source "board/barco/platinum/Kconfig" source "board/barco/platinum/Kconfig"
source "board/barco/titanium/Kconfig" source "board/barco/titanium/Kconfig"
source "board/boundary/a/Kconfig" source "board/boundary/a/Kconfig"
source "board/boundary/acl/Kconfig"
source "board/boundary/nitrogen6x/Kconfig" source "board/boundary/nitrogen6x/Kconfig"
source "board/boundary/ys/Kconfig" source "board/boundary/ys/Kconfig"
source "board/bticino/mamoj/Kconfig" source "board/bticino/mamoj/Kconfig"
......
board/boundary/acl/Kconfig 0 → 100644
+ 14
− 0
View file @ b17a1f63
if TARGET_ACL
config SYS_BOARD
default "acl"
config SYS_VENDOR
default "boundary"
config SYS_CONFIG_NAME
default "acl"
source "board/boundary/common/Kconfig"
endif
board/boundary/acl/MAINTAINERS 0 → 100644
+ 6
− 0
View file @ b17a1f63
ACL BOARD
M: Troy Kisky <troy.kisky@boundarydevices.com>
S: Maintained
F: board/boundary/acl/
F: include/configs/acl.h
F: configs/acl_defconfig
board/boundary/acl/Makefile 0 → 100644
+ 7
− 0
View file @ b17a1f63
#
# Copyright (C) 2016, Boundary Devices <info@boundarydevices.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := acl.o
board/boundary/acl/acl.c 0 → 100644
+ 534
− 0
View file @ b17a1f63
/*
* Copyright (C) 2016, Boundary Devices <info@boundarydevices.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
#include <malloc.h>
#include <asm/arch/mx6-pins.h>
#include <linux/errno.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/fbpanel.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/spi.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mxc_hdmi.h>
#include <i2c.h>
#include <input.h>
#include <splash.h>
#include <usb/ehci-ci.h>
#include "../common/bd_common.h"
#include "../common/padctrl.h"
DECLARE_GLOBAL_DATA_PTR;
#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define OUTPUT_40OHM (PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
#define RGB_PAD_CTRL PAD_CTL_DSE_120ohm
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_HYS | PAD_CTL_SRE_FAST)
static const iomux_v3_cfg_t init_pads[] = {
/* Buzzer */
#define GP_GPIO3_CLKO2 IMX_GPIO_NR(1, 6)
IOMUX_PAD_CTRL(GPIO_3__GPIO1_IO03, WEAK_PULLDN),
/* ECSPI1 */
IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
#define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19)
IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP),
/* ECSPI2 */
IOMUX_PAD_CTRL(CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
#define GP_ECSPI2_NOR_CS0 IMX_GPIO_NR(5, 29)
IOMUX_PAD_CTRL(CSI0_DAT11__GPIO5_IO29, WEAK_PULLUP),
#define GP_ECSPI2_NOR_CS1 IMX_GPIO_NR(2, 27)
IOMUX_PAD_CTRL(EIM_LBA__GPIO2_IO27, WEAK_PULLUP),
/* ECSPI4 */
IOMUX_PAD_CTRL(EIM_D21__ECSPI4_SCLK, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D28__ECSPI4_MOSI, SPI_PAD_CTRL),
#ifndef CONFIG_MX6S
/* ECSPI5 */
IOMUX_PAD_CTRL(SD2_CLK__ECSPI5_SCLK, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_CMD__ECSPI5_MOSI, SPI_PAD_CTRL),
IOMUX_PAD_CTRL(SD2_DAT0__ECSPI5_MISO, SPI_PAD_CTRL),
#define GP_ECSPI5_NOR_CS IMX_GPIO_NR(1, 14)
IOMUX_PAD_CTRL(SD2_DAT1__GPIO1_IO14, WEAK_PULLUP),
#endif
/* ENET pads that don't change for PHY reset */
IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, PAD_CTRL_ENET_TX),
IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, PAD_CTRL_ENET_TX),
#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 27)
IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, WEAK_PULLUP),
#define GPIRQ_ENET_PHY IMX_GPIO_NR(1, 28)
IOMUX_PAD_CTRL(ENET_TX_EN__GPIO1_IO28, WEAK_PULLUP),
/* Fan */
#define GPIRQ_FAN IMX_GPIO_NR(7, 12)
IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, WEAK_PULLDN),
#define GP_FAN_ON IMX_GPIO_NR(1, 8)
IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, WEAK_PULLDN),
/* Hogs */
#define GP_TP73 IMX_GPIO_NR(1, 9)
IOMUX_PAD_CTRL(GPIO_9__GPIO1_IO09, WEAK_PULLUP),
/* I2C2 RV4172 RTC */
#define GPIRQ_RTC_RV4162 IMX_GPIO_NR(4, 6)
IOMUX_PAD_CTRL(KEY_COL0__GPIO4_IO06, WEAK_PULLUP),
/* I2C3 ADS7924 ADC */
#define GPIRQ_ADC_INTR IMX_GPIO_NR(3, 14)
IOMUX_PAD_CTRL(EIM_DA14__GPIO3_IO14, WEAK_PULLUP),
#define GP_ADC_RESET IMX_GPIO_NR(3, 15)
IOMUX_PAD_CTRL(EIM_DA15__GPIO3_IO15, WEAK_PULLDN),
/* I2C3 ADT75 Temperature */
#define GPIRQ_TEMP_ALERT IMX_GPIO_NR(1, 4)
IOMUX_PAD_CTRL(GPIO_4__GPIO1_IO04, WEAK_PULLUP),
/* Motors */
#define GP_DOOR1 IMX_GPIO_NR(2, 24)
IOMUX_PAD_CTRL(EIM_CS1__GPIO2_IO24, WEAK_PULLDN),
#define GP_MOTOR_HOME1A IMX_GPIO_NR(2, 23)
IOMUX_PAD_CTRL(EIM_CS0__GPIO2_IO23, WEAK_PULLDN),
#define GP_MOTOR_HOME1B IMX_GPIO_NR(2, 25)
IOMUX_PAD_CTRL(EIM_OE__GPIO2_IO25, WEAK_PULLDN),
#define GP_MOTOR_HOME2 IMX_GPIO_NR(2, 26)
IOMUX_PAD_CTRL(EIM_RW__GPIO2_IO26, WEAK_PULLDN),
#define GP_STEP1_RESET IMX_GPIO_NR(3, 8)
IOMUX_PAD_CTRL(EIM_DA8__GPIO3_IO08, WEAK_PULLDN),
#define GP_STEP1_BUSY IMX_GPIO_NR(3, 9)
IOMUX_PAD_CTRL(EIM_DA9__GPIO3_IO09, WEAK_PULLDN),
#define GP_STEP1_FLAG IMX_GPIO_NR(3, 10)
IOMUX_PAD_CTRL(EIM_DA10__GPIO3_IO10, WEAK_PULLDN),
#define GP_STEP1_SW IMX_GPIO_NR(3, 11)
IOMUX_PAD_CTRL(EIM_DA11__GPIO3_IO11, WEAK_PULLDN),
#define GP_STEP2_RESET IMX_GPIO_NR(2, 31)
IOMUX_PAD_CTRL(EIM_EB3__GPIO2_IO31, WEAK_PULLDN),
#define GP_STEP2_BUSY IMX_GPIO_NR(5, 0)
IOMUX_PAD_CTRL(EIM_WAIT__GPIO5_IO00, WEAK_PULLDN),
#define GP_STEP2_FLAG IMX_GPIO_NR(6, 31)
IOMUX_PAD_CTRL(EIM_BCLK__GPIO6_IO31, WEAK_PULLDN),
#define GP_STEP2_SW IMX_GPIO_NR(2, 28)
IOMUX_PAD_CTRL(EIM_EB0__GPIO2_IO28, WEAK_PULLDN),
/* PWM1 - Step motor 1 */
IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, WEAK_PULLDN),
/* PWM2 - Step motor 2 */
IOMUX_PAD_CTRL(SD1_DAT2__GPIO1_IO19, WEAK_PULLDN),
/* PWM3 - Backlight on RGB connector: J15 */
#define GP_BACKLIGHT_RGB IMX_GPIO_NR(1, 17)
IOMUX_PAD_CTRL(SD1_DAT1__GPIO1_IO17, WEAK_PULLDN),
/* PWM4 - Cartridge optics */
IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, WEAK_PULLDN),
/* reg_usbotg_vbus */
#define GP_REG_USBOTG IMX_GPIO_NR(3, 22)
IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, WEAK_PULLDN),
/* Printer */
#define GP_PRINT_BDCAY IMX_GPIO_NR(2, 22)
IOMUX_PAD_CTRL(EIM_A16__GPIO2_IO22, WEAK_PULLUP),
#define GP_PRINT_ADCAY IMX_GPIO_NR(2, 21)
IOMUX_PAD_CTRL(EIM_A17__GPIO2_IO21, WEAK_PULLUP),
#define GP_PRINT_TOFF IMX_GPIO_NR(2, 20)
IOMUX_PAD_CTRL(EIM_A18__GPIO2_IO20, WEAK_PULLUP),
#define GP_PRINT_ATE IMX_GPIO_NR(2, 19)
IOMUX_PAD_CTRL(EIM_A19__GPIO2_IO19, WEAK_PULLUP),
#define GP_PRINT_SLEEP_N IMX_GPIO_NR(2, 18)
IOMUX_PAD_CTRL(EIM_A20__GPIO2_IO18, WEAK_PULLUP),
#define GP_PRINT_BEN IMX_GPIO_NR(2, 17)
IOMUX_PAD_CTRL(EIM_A21__GPIO2_IO17, WEAK_PULLUP),
#define GP_PRINT_BPH IMX_GPIO_NR(2, 16)
IOMUX_PAD_CTRL(EIM_A22__GPIO2_IO16, WEAK_PULLUP),
#define GP_PRINT_AEN IMX_GPIO_NR(6, 6)
IOMUX_PAD_CTRL(EIM_A23__GPIO6_IO06, WEAK_PULLUP),
#define GP_PRINT_APH IMX_GPIO_NR(5, 4)
IOMUX_PAD_CTRL(EIM_A24__GPIO5_IO04, WEAK_PULLUP),
#define GP_PRINT_STROBE1 IMX_GPIO_NR(3, 0)
IOMUX_PAD_CTRL(EIM_DA0__GPIO3_IO00, WEAK_PULLUP),
#define GP_PRINT_STROBE2 IMX_GPIO_NR(3, 1)
IOMUX_PAD_CTRL(EIM_DA1__GPIO3_IO01, WEAK_PULLUP),
#define GP_PRINT_STROBE3 IMX_GPIO_NR(3, 2)
IOMUX_PAD_CTRL(EIM_DA2__GPIO3_IO02, WEAK_PULLUP),
#define GP_PRINT_STROBE4 IMX_GPIO_NR(3, 3)
IOMUX_PAD_CTRL(EIM_DA3__GPIO3_IO03, WEAK_PULLUP),
#define GP_PRINT_STROBE5 IMX_GPIO_NR(3, 4)
IOMUX_PAD_CTRL(EIM_DA4__GPIO3_IO04, WEAK_PULLUP),
#define GP_PRINT_STROBE6 IMX_GPIO_NR(3, 5)
IOMUX_PAD_CTRL(EIM_DA5__GPIO3_IO05, WEAK_PULLUP),
#define GP_PRINT_LATCH_B IMX_GPIO_NR(3, 7)
IOMUX_PAD_CTRL(EIM_DA7__GPIO3_IO07, WEAK_PULLUP),
#define GP_PRINT_ALERT IMX_GPIO_NR(5, 20)
IOMUX_PAD_CTRL(CSI0_DATA_EN__GPIO5_IO20, WEAK_PULLUP),
#define GP_PRINT_TRQ0 IMX_GPIO_NR(5, 22)
IOMUX_PAD_CTRL(CSI0_DAT4__GPIO5_IO22, WEAK_PULLUP),
#define GP_PRINT_TRQ1 IMX_GPIO_NR(5, 23)
IOMUX_PAD_CTRL(CSI0_DAT5__GPIO5_IO23, WEAK_PULLUP),
#define GP_PRINT_FAULT IMX_GPIO_NR(5, 24)
IOMUX_PAD_CTRL(CSI0_DAT6__GPIO5_IO24, WEAK_PULLUP),
#define GP_PRINT_DO IMX_GPIO_NR(1, 13)
IOMUX_PAD_CTRL(SD2_DAT2__GPIO1_IO13, WEAK_PULLUP),
#define GP_PAPER_OUT IMX_GPIO_NR(1, 12)
IOMUX_PAD_CTRL(SD2_DAT3__GPIO1_IO12, WEAK_PULLUP),
#define GP_STAT_LED1 IMX_GPIO_NR(3, 29)
IOMUX_PAD_CTRL(EIM_D29__GPIO3_IO29, WEAK_PULLDN),
#define GP_STAT_LED2 IMX_GPIO_NR(2, 29)
IOMUX_PAD_CTRL(EIM_EB1__GPIO2_IO29, WEAK_PULLDN),
#define GP_DRDY IMX_GPIO_NR(7, 1)
IOMUX_PAD_CTRL(SD3_DAT4__GPIO7_IO01, WEAK_PULLDN),
/* Scanner */
#define GP_SCAN_AIM IMX_GPIO_NR(5, 19)
IOMUX_PAD_CTRL(CSI0_MCLK__GPIO5_IO19, WEAK_PULLUP),
#define GP_SCAN_TRIG IMX_GPIO_NR(5, 18)
IOMUX_PAD_CTRL(CSI0_PIXCLK__GPIO5_IO18, WEAK_PULLUP),
#define GP_SCAN_STA IMX_GPIO_NR(6, 2)
IOMUX_PAD_CTRL(CSI0_DAT16__GPIO6_IO02, WEAK_PULLDN),
#define GP_SCAN_DNLOAD IMX_GPIO_NR(6, 3)
IOMUX_PAD_CTRL(CSI0_DAT17__GPIO6_IO03, WEAK_PULLUP),
/* Solenoids */
#define GP_SOLENOID1_ON IMX_GPIO_NR(4, 5)
IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, WEAK_PULLUP),
#define GP_SOLENOID2_ON IMX_GPIO_NR(1, 7)
IOMUX_PAD_CTRL(GPIO_7__GPIO1_IO07, WEAK_PULLUP),
#define GP_SOLENOID3_ON IMX_GPIO_NR(1, 2)
IOMUX_PAD_CTRL(GPIO_2__GPIO1_IO02, WEAK_PULLUP),
#define GP_SPARE IMX_GPIO_NR(1, 16)
IOMUX_PAD_CTRL(SD1_DAT0__GPIO1_IO16, WEAK_PULLUP),
#define GPIRQ_SOLENOID_FAULT IMX_GPIO_NR(7, 13)
IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, WEAK_PULLUP),
/* Touch */
#define GP_TOUCH_WAKE IMX_GPIO_NR(4, 11)
IOMUX_PAD_CTRL(KEY_ROW2__GPIO4_IO11, WEAK_PULLUP),
#define GPIRQ_TOUCH IMX_GPIO_NR(4, 10)
IOMUX_PAD_CTRL(KEY_COL2__GPIO4_IO10, WEAK_PULLDN),
/* UART1 */
IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
/* UART2 */
#ifndef CONFIG_SILENT_UART
IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
#else
IOMUX_PAD_CTRL(EIM_D26__GPIO3_IO26, UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D27__GPIO3_IO27, UART_PAD_CTRL),
#endif
/* UART3 */
IOMUX_PAD_CTRL(EIM_D24__UART3_TX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D25__UART3_RX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D23__UART3_CTS_B, UART_PAD_CTRL),
IOMUX_PAD_CTRL(EIM_D31__UART3_RTS_B, UART_PAD_CTRL),
/* UART5 */
IOMUX_PAD_CTRL(KEY_COL1__UART5_TX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(KEY_ROW1__UART5_RX_DATA, UART_PAD_CTRL),
IOMUX_PAD_CTRL(KEY_ROW4__UART5_CTS_B, UART_PAD_CTRL),
IOMUX_PAD_CTRL(CSI0_DAT18__UART5_RTS_B, UART_PAD_CTRL),
/* USBH1 */
IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
/* USBOTG */
IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
/* USDHC3 - sdcard */
IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
#define GP_USDHC3_CD IMX_GPIO_NR(7, 0)
IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, WEAK_PULLUP),
/* USDHC4 - sdcard */
IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
IOMUX_PAD_CTRL(SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
#define GP_EMMC_RESET IMX_GPIO_NR(2, 6)
IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, WEAK_PULLUP),
};
#ifdef CONFIG_CMD_FBPANEL
static const iomux_v3_cfg_t rgb666_pads[] = {
IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL), /* DRDY */
IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL), /* HSYNC */
IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL), /* VSYNC */
IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
};
static const iomux_v3_cfg_t rgb24_pads[] = {
IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
};
#endif
static const iomux_v3_cfg_t rgb_gpio_pads[] = {
IOMUX_PAD_CTRL(DI0_DISP_CLK__GPIO4_IO16, WEAK_PULLUP),
IOMUX_PAD_CTRL(DI0_PIN15__GPIO4_IO17, WEAK_PULLUP),
IOMUX_PAD_CTRL(DI0_PIN2__GPIO4_IO18, WEAK_PULLUP),
IOMUX_PAD_CTRL(DI0_PIN3__GPIO4_IO19, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT0__GPIO4_IO21, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT1__GPIO4_IO22, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT2__GPIO4_IO23, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT5__GPIO4_IO26, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT6__GPIO4_IO27, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT7__GPIO4_IO28, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT8__GPIO4_IO29, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT9__GPIO4_IO30, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT10__GPIO4_IO31, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT11__GPIO5_IO05, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT12__GPIO5_IO06, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT13__GPIO5_IO07, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT14__GPIO5_IO08, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT15__GPIO5_IO09, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT16__GPIO5_IO10, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT17__GPIO5_IO11, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT18__GPIO5_IO12, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT19__GPIO5_IO13, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT20__GPIO5_IO14, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT21__GPIO5_IO15, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT22__GPIO5_IO16, WEAK_PULLUP),
IOMUX_PAD_CTRL(DISP0_DAT23__GPIO5_IO17, WEAK_PULLUP),
};
static const struct i2c_pads_info i2c_pads[] = {
/* I2C2 - touch / RTC / ADC */
I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
/* I2C3 - ADC / temperature */
I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
};
#define I2C_BUS_CNT 2
#ifdef CONFIG_USB_EHCI_MX6
int board_ehci_power(int port, int on)
{
if (port)
return 0;
gpio_set_value(GP_REG_USBOTG, on);
return 0;
}
#endif
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg board_usdhc_cfg[] = {
{.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 4, .gp_cd = GP_USDHC3_CD},
{.esdhc_base = USDHC4_BASE_ADDR, .bus_width = 8, .gp_reset = GP_EMMC_RESET},
};
#endif
#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : -1;
}
#endif
#ifdef CONFIG_CMD_FBPANEL
void board_enable_lcd(const struct display_info_t *di, int enable)
{
if (enable) {
SETUP_IOMUX_PADS(rgb666_pads);
if (di->pixfmt == IPU_PIX_FMT_RGB24)
SETUP_IOMUX_PADS(rgb24_pads);
mdelay(100); /* let panel sync up before enabling backlight */
gpio_direction_output(GP_BACKLIGHT_RGB, enable);
} else {
gpio_direction_output(GP_BACKLIGHT_RGB, enable);
SETUP_IOMUX_PADS(rgb_gpio_pads);
}
}
void board_pre_enable(const struct display_info_t *di)
{
SETUP_IOMUX_PADS(rgb666_pads);
}
static const struct display_info_t displays[] = {
VD_ASIT500MA6F5D(LCD, NULL, 1, 0x40),
};
#define display_cnt ARRAY_SIZE(displays)
#else
#define displays NULL
#define display_cnt 0
#endif
static const unsigned short gpios_out_low[] = {
GP_RGMII_PHY_RESET,
GP_ADC_RESET,
GP_BACKLIGHT_RGB,
GP_EMMC_RESET,
GP_FAN_ON,
GP_GPIO3_CLKO2,
GP_PRINT_SLEEP_N,
GP_PRINT_STROBE1,
GP_PRINT_STROBE2,
GP_PRINT_STROBE3,
GP_PRINT_STROBE4,
GP_PRINT_STROBE5,
GP_PRINT_STROBE6,
GP_REG_USBOTG,
GP_SCAN_STA,
GP_SOLENOID1_ON,
GP_SOLENOID2_ON,
GP_SOLENOID3_ON,
GP_STAT_LED1,
GP_STAT_LED2,
GP_STEP1_RESET,
GP_STEP2_RESET,
GP_SPARE,
};
static const unsigned short gpios_out_high[] = {
GP_ECSPI1_NOR_CS,
GP_ECSPI2_NOR_CS0,
GP_ECSPI2_NOR_CS1,
#ifndef CONFIG_MX6S
GP_ECSPI5_NOR_CS,
#endif
GP_SCAN_AIM,
GP_SCAN_DNLOAD,
GP_SCAN_TRIG,
GP_TOUCH_WAKE,
};
static const unsigned short gpios_in[] = {
GPIRQ_ADC_INTR,
GPIRQ_ENET_PHY,
GPIRQ_FAN,
GPIRQ_RTC_RV4162,
GPIRQ_SOLENOID_FAULT,
GPIRQ_TEMP_ALERT,
GPIRQ_TOUCH,
GP_DOOR1,
GP_MOTOR_HOME1A,
GP_MOTOR_HOME1B,
GP_MOTOR_HOME2,
GP_PAPER_OUT,
GP_PRINT_ALERT,
GP_PRINT_DO,
GP_PRINT_FAULT,
GP_PRINT_LATCH_B,
GP_STEP1_BUSY,
GP_STEP1_FLAG,
GP_STEP1_SW,
GP_STEP2_BUSY,
GP_STEP2_FLAG,
GP_STEP2_SW,
GP_USDHC3_CD,
};
int board_early_init_f(void)
{
set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
SETUP_IOMUX_PADS(init_pads);
SETUP_IOMUX_PADS(rgb_gpio_pads);
return 0;
}
int board_init(void)
{
common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
displays, display_cnt, 0);
return 0;
}
const struct button_key board_buttons[] = {
{"tp73", GP_TP73, 't', 1},
{NULL, 0, 0, 0},
};
#ifdef CONFIG_CMD_BMODE
const struct boot_mode board_boot_modes[] = {
/* 4 bit bus width */
{"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
/* 8 bit bus width */
{"mmc1", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
{NULL, 0},
};
#endif
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/*
* Copyright (C) 2016 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* NC YET */
#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42740304
#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x026e0265
#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x02750306
#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x02720244
#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x463d4041
#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x42413c47
#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x37414441
#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x4633473b
#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0025001f
#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x00290027
#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x001f002b
#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x000f0029
#define WALAT 1
#include "../common/mx6/ddr-setup.cfg"
#define RANK 0
#define BUS_WIDTH 64
/* This configuration not yet produced */
#include "../common/mx6/1066mhz_256mx16.cfg"
#include "../common/mx6/clocks.cfg"
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/*
* Copyright (C) 2016 Boundary Devices
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer doc/README.imximage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
#define __ASSEMBLY__
#include <config.h>
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
/* 5 board sample */
#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42380238
#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x02210222
#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x4445484e
#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x36342c2b
#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x003d0045
#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x0034003c
#define WALAT 1
#include "../common/mx6/ddr-setup.cfg"
#define RANK 0
#define BUS_WIDTH 32
/* H5TC2G63FFR-PBA */
#include "../common/mx6/800mhz_128mx16.cfg"
#include "../common/mx6/clocks.cfg"
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CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_ACL=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/acl/acl2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"acl_q2g\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_FASTBOOT_BUF_SIZE=0x26000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Boundary"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
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CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_TARGET_ACL=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/acl/acl512m.cfg,MX6S,DDR_MB=512,DEFCONFIG=\"acl_s512m\""
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_SATA=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_FASTBOOT_BUF_SIZE=0x26000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Boundary"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_OF_LIBFDT=y
include/configs/acl.h 0 → 100644
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View file @ b17a1f63
/*
* Copyright (C) 2016, Boundary Devices <info@boundarydevices.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "mx6_common.h"
#define CONFIG_MACH_TYPE 3769
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define BD_I2C_MASK 6
#include "boundary.h"
#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
#endif /* __CONFIG_H */
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