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Commit ad75d442 authored by Prabhakar Kushwaha's avatar Prabhakar Kushwaha Committed by Andy Fleming
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powerpc/mpc85xx:Add debugger support for e500v2 SoC


Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).

So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Please refer doc/README.mpc85xx for more information

Signed-off-by: default avatarRadu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: default avatarPrabhakar Kushwaha <prabhakar@freescale.com>
parent d16a37b8
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...@@ -122,6 +122,7 @@ ...@@ -122,6 +122,7 @@
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2 #define CONFIG_FSL_SATA_V2
...@@ -138,6 +139,7 @@ ...@@ -138,6 +139,7 @@
#elif defined(CONFIG_P1011) #elif defined(CONFIG_P1011)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -149,6 +151,7 @@ ...@@ -149,6 +151,7 @@
#elif defined(CONFIG_P1012) #elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -163,6 +166,7 @@ ...@@ -163,6 +166,7 @@
#elif defined(CONFIG_P1013) #elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2 #define CONFIG_FSL_SATA_V2
...@@ -175,6 +179,7 @@ ...@@ -175,6 +179,7 @@
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_FSL_SDHC_V2_3 #define CONFIG_FSL_SDHC_V2_3
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2 #define CONFIG_FSL_SATA_V2
...@@ -190,6 +195,7 @@ ...@@ -190,6 +195,7 @@
#elif defined(CONFIG_P1015) #elif defined(CONFIG_P1015)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -201,6 +207,7 @@ ...@@ -201,6 +207,7 @@
#elif defined(CONFIG_P1016) #elif defined(CONFIG_P1016)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -228,6 +235,7 @@ ...@@ -228,6 +235,7 @@
#elif defined(CONFIG_P1020) #elif defined(CONFIG_P1020)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -238,6 +246,7 @@ ...@@ -238,6 +246,7 @@
#elif defined(CONFIG_P1021) #elif defined(CONFIG_P1021)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -251,6 +260,7 @@ ...@@ -251,6 +260,7 @@
#elif defined(CONFIG_P1022) #elif defined(CONFIG_P1022)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2 #define CONFIG_FSL_SATA_V2
...@@ -276,6 +286,7 @@ ...@@ -276,6 +286,7 @@
#elif defined(CONFIG_P1024) #elif defined(CONFIG_P1024)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -287,6 +298,7 @@ ...@@ -287,6 +298,7 @@
#elif defined(CONFIG_P1025) #elif defined(CONFIG_P1025)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2 #define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM #define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
...@@ -301,6 +313,7 @@ ...@@ -301,6 +313,7 @@
#elif defined(CONFIG_P2010) #elif defined(CONFIG_P2010)
#define CONFIG_MAX_CPUS 1 #define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
...@@ -309,6 +322,7 @@ ...@@ -309,6 +322,7 @@
#elif defined(CONFIG_P2020) #elif defined(CONFIG_P2020)
#define CONFIG_MAX_CPUS 2 #define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12 #define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_SYS_FSL_SEC_COMPAT 2 #define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
......
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