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Commit a49716aa authored by Allen Martin's avatar Allen Martin Committed by Albert ARIBAUD
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tegra20: move SDRAM param save to later in boot


Move warmboot_save_sdram_params() to later in the boot sequence.  This
code relies on devicetree to get the address of the memory controller
and with upcoming changes for SPL boot it gets called early in the
boot process when devicetree is not initialized yet.

Signed-off-by: default avatarAllen Martin <amartin@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@wwwdotorg.org>
Tested-by: default avatarThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: default avatarTom Warren <twarren@nvidia.com>
parent 984df4ec
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...@@ -345,11 +345,6 @@ void init_pmc_scratch(void) ...@@ -345,11 +345,6 @@ void init_pmc_scratch(void)
/* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
odmdata = get_odmdata(); odmdata = get_odmdata();
writel(odmdata, &pmc->pmc_scratch20); writel(odmdata, &pmc->pmc_scratch20);
#ifdef CONFIG_TEGRA20_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
#endif
} }
void tegra20_start(void) void tegra20_start(void)
......
...@@ -133,6 +133,9 @@ int board_init(void) ...@@ -133,6 +133,9 @@ int board_init(void)
#endif #endif
#ifdef CONFIG_TEGRA20_LP0 #ifdef CONFIG_TEGRA20_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
/* prepare the WB code to LP0 location */ /* prepare the WB code to LP0 location */
warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
#endif #endif
......
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