arm: socfpga: fix up a questionable macro for SDMMC

Move the macro into the socfpga_dwmci_clksel().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Marek Vasut <marex@denx.de>
[fix parenthesis in the sdmmc_mask]

arch/arm/mach-socfpga/include/mach/system_manager.h

@@ -129,9 +129,13 @@ struct socfpga_system_manager {
 #define SYSMGR_FPGAINTF_NAND	(1 << 4)
 #define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
 
-/* FIXME: This is questionable macro. */
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
-	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	3
+#else
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT	4
+#endif
+
+#define SYSMGR_SDMMC_DRVSEL_SHIFT	0
 
 /* EMAC Group Bit definitions */
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0

drivers/mmc/socfpga_dw_mmc.c

@@ -33,6 +33,8 @@ struct dwmci_socfpga_priv_data {
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
 	struct dwmci_socfpga_priv_data *priv = host->priv;
+	u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
+			 ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
 
 	/* Disable SDMMC clock. */
 	clrbits_le32(&clock_manager_base->per_pll.en,
@@ -40,8 +42,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
-	writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
-		&system_manager_base->sdmmcgrp_ctrl);
+	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
 		readl(&system_manager_base->sdmmcgrp_ctrl));