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Commit 9fd11c7a authored by Simon Glass's avatar Simon Glass Committed by Bin Meng
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x86: ivybridge: Move GPIO init to the LPC init() method


This init can happen in the driver also. Move it.

Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
parent fcd30cdf
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...@@ -278,10 +278,6 @@ int print_cpuinfo(void) ...@@ -278,10 +278,6 @@ int print_cpuinfo(void)
gd->arch.pei_boot_mode = boot_mode; gd->arch.pei_boot_mode = boot_mode;
/* TODO: Move this to the board or driver */
x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
/* Print processor name */ /* Print processor name */
name = cpu_get_name(processor_name); name = cpu_get_name(processor_name);
printf("CPU: %s\n", name); printf("CPU: %s\n", name);
......
...@@ -623,6 +623,9 @@ static int bd82x6x_lpc_early_init(struct udevice *dev) ...@@ -623,6 +623,9 @@ static int bd82x6x_lpc_early_init(struct udevice *dev)
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
return 0; return 0;
} }
......
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