Skip to content
Snippets Groups Projects
Commit 990dba64 authored by Patrice Chotard's avatar Patrice Chotard Committed by Tom Rini
Browse files

clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value


PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
  00: PLLSAIP = 2
  01: PLLSAIP = 4
  10: PLLSAIP = 6
  11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: default avatarPatrice Chotard <patrice.chotard@st.com>
parent a93feb2e
No related branches found
No related tags found
No related merge requests found
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment